Superior n-MOSFET Performance by Optimal Stress Design

Liao, Ming-Han; Yeh, Lingyen; Lee, T.-L.; C, Liu; Liang, Mong–Song

doi:10.1109/led.2008.918420

Cited by 16 publications

(6 citation statements)

References 8 publications

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“…It indicates that the reduction W can effectively enhance carrier mobility. It could be attributed the increase of tensile stress along channel width direction [8]. Furthermore, it is also found that the strain effects of SMT and strain contact etch stop layer (CESL) are similar as W scaled down.…”

Section: Resultsmentioning

confidence: 90%

Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

Kuo¹,

Wu²,

Lin³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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Section: Resultsmentioning

confidence: 90%

Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

Kuo¹,

Wu²,

Lin³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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“…All simulated drive current differences in this work are due to the stress. Stress impact on device mobility is captured using a model of related strained Si theory [12,13].…”

Section: Methodsmentioning

confidence: 99%

A non-linear analytic stress model for the analysis on the stress interaction between TSVs

Liao

Kao²,

Huang³

2015

AUSMT

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Thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (∼18 ppm/•C) and silicon (∼2.8 ppm/•C) when the structure is exposed to a thermal budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to induce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to result in large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the finite element method and Mohr's circle analysis. The stress characteristics are also measured by the atomic force microscope-raman technique at a nanometer level resolution. This nonlinear stress model for the strong interactions between TSVs results in an electron mobility change ~2-6% smaller than that resulting from a model that only considers the linear stress superposition principle.

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“…All simulated drive current differences in this work are due to the stress. Stress impact on the device mobility is captured with the model of related strained Si theory [12][13].…”

Section: IImentioning

confidence: 99%

The demonstration of nonlinear analytic model for the strain field induced by thermal copper filled TSVs (through silicon via)

Liao¹,

Chen²,

Lee³

et al. 2013

2013 E-Manufacturing &Amp; Design Collaboration Symposium (eMDC)

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The thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (-18 ppm/oC) and silicon (-2.8 ppm/oC) when the structure is exposed to a thennal ramp budget in the three dimensional integrated circuit (3D\C) process. These thermal expansion stresses are highly enough to introduce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to have large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the [mite element method and the analysis of the Mohr's circle. The characteristics of stress are also measured by the atomic force microscope-raman technique with nanometer level space resolution. The change of the electron mobility with the consideration of this nonlinear stress model for the strong interactions between TSVs is �2-6% smaller than it with the consideration of the linear stress superposition principle only.I.

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Superior n-MOSFET Performance by Optimal Stress Design

Cited by 16 publications

References 8 publications

Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

A non-linear analytic stress model for the analysis on the stress interaction between TSVs

The demonstration of nonlinear analytic model for the strain field induced by thermal copper filled TSVs (through silicon via)

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