Supercomputing with commodity CPUs

Rajovic, Nikola; Carpenter, Paul; Gelado, Isaac; Puzovic, Nikola; Ramírez, Alex; Valero, Mateo

doi:10.1145/2503210.2503281

Cited by 99 publications

(29 citation statements)

References 22 publications

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“…The chosen system architecture for the SoC is based on ARMv8-A Cortex 64-bit [26] processors due to its lowpower consumption and reduced cost. Although ARM-based application processors can be found in about an 85% share of mobile devices [27] there has been a recent strong interest for the use of ARM cores also in high-performance computing [28] [29]. ARM expects that '25% share of servers shipped in 2020 will be using ARM-based chips."…”

Section: Server and Rack Architecturementioning

confidence: 99%

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Vega

Zazo²,

Meyer

et al. 2017

2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference On

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Traditional data centers are designed with a rigid architecture of fit-for-purpose servers that provision resources beyond the average workload in order to deal with occasional peaks of data. Heterogeneous data centers are pushing towards more cost-efficient architectures with better resource provisioning. In this paper we study the feasibility of using disaggregated architectures for intensive data applications, in contrast to the monolithic approach of server-oriented architectures. Particularly, we have tested a proactive network analysis system in which the workload demands are highly variable. In the context of the dReDBox disaggregated architecture, the results show that the overhead caused by using remote memory resources is significant, between 66% and 80%, but we have also observed that the memory usage is one order of magnitude higher for the stress case with respect to average workloads. Therefore, dimensioning memory for the worst case in conventional systems will result in a notable waste of resources. Finally, we found that, for the selected use case, parallelism is limited by memory. Therefore, using a disaggregated architecture will allow for increased parallelism, which, at the same time, will mitigate the overhead caused by remote memory.

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Section: Server and Rack Architecturementioning

confidence: 99%

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Vega

Zazo²,

Meyer

et al. 2017

2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference On

View full text Add to dashboard Cite

show abstract

“…Since Android can execute Java code, we simply require designers to apply their tasks in Java. While scheduling tasks on phones are essential, we have to note that they're personal products [3]. First, you should make sure that whenever a user selects to make use of her phone, CWC stops the execution from the last designated task to that particular phone so they won't negatively change up the finishconsumer experience.…”

Section: Proposed Workmentioning

confidence: 99%

Balancing Load in Smartphone’s

Podaralla¹

2017

ijecs

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The growing computing abilities of wise phones, these idle phones constitute a significant computing infrastructure. Therefore, to have an enterprise which gives its employees with wise phones, we reason that a computing infrastructure that leverages idle wise phones being billed overnight is definitely an energyefficient and price-effective option to running certain tasks on traditional servers. Every evening, many wise phones are blocked right into a source of energy for recharging battery. While parallel execution models and schedulers exists for servers, wise phones face a distinctive group of technical challenges because of the heterogeneity in CPU clock speed, variability in network bandwidth, minimizing availability than servers.Within this paper, we address a number of these challenges to build up CWC-a distributed computing infrastructure using wise phones. We next investigate whether continuous usage of the CPU affects the CPU efficiency. Our evaluations utilizing a test bed of 18 Android phones reveal that CWC's scheduler yields a make span that's 1.6x quicker than other simpler approaches. We implement and evaluate a prototype of CWC that utilizes a manuscript scheduling formula to reduce the make length of some computing tasks.

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“…Our characterization experiments focus on a P. Moorthy, N. Kapre single chip and measure raw compute throughput, memory performance as well as MPI support for these systems. Recent academic studies have examined the feasibility of HPC systems based on mobile SoCs [3] for HPC-oriented workloads and investigated the status of networking support in these SoCs. Additionally, there are many contemporary hobbyist clusters built from Apple TV [4], Raspberry Pi [5], and Beagleboard xM [6] that use off-the-shelf devices for delivering proofof-concept systems with high power efficiency.…”

Section: Microbenchmarking Cots Soc Platformsmentioning

confidence: 99%

A Case for Embedded FPGA-based SoCs in Energy-Efficient Acceleration of Graph Problems

Kapre

Moorthy

2015

JSFI

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Sparse graph problems are notoriously hard to accelerate on conventional platforms due to irregular memory access patterns resulting in underutilization of memory bandwidth. These bottlenecks on traditional x86-based systems mean that sparse graph problems scale very poorly, both in terms of performance and power efficiency. A cluster of embedded SoCs (systems-on-chip) with closely-coupled FPGA accelerators can support distributed memory access with better matched low-power processing. We first conduct preliminary experiments across a range of COTS (commercial off-the-shelf) embedded SoCs to establish promise for energy-efficiency acceleration of sparse problems. We select the Xilinx Zynq SoC with FPGA accelerators to construct a prototype 32-node Beowulf cluster. We develop specialized MPI routines and memory DMA offload engines to support irregular communication efficiently. In this setup, we use the ARM processor as a data marshaller for local DMA traffic as well as remote MPI traffic while the FPGA may be used as a programmable accelerator. Across a set of benchmark graphs, we show that 32-node embedded SoC cluster can exceed the energy efficiency of an Intel E5-2407 by as much as 1.7× at a total graph processing capacity of 91-95 MTEPS for graphs as large as 32 million nodes and edges.

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Supercomputing with commodity CPUs

Cited by 99 publications

References 22 publications

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Balancing Load in Smartphone’s

A Case for Embedded FPGA-based SoCs in Energy-Efficient Acceleration of Graph Problems

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