Supercomputers-beyond today's supercomputers

Bell, Thomas E.

doi:10.1109/6.155714

Cited by 8 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…

these are the Intel Touchstone Delta [13], the Intel Paragon XP/S [12], the Tera Computer System [14], the Cray T-3D system [15], the Fujitsu AP-100 [17], the Parsytec GC [16], the PASM [18], and the Sanyo Edden/Cyberflow system [17].Most of the commercial systems mentioned above are MIMD machines. As a partitionable architecture, the MIMD mesh has the advantage of supporting multiple tasks, each of which can be assigned an independent submesh, for execution by the host operating system.

…”

mentioning

confidence: 99%

See 1 more Smart Citation

Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability

Sharma

Pradhan

1996

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

“…

…”

mentioning

confidence: 99%

“…these are the Intel Touchstone Delta [13], the Intel Paragon XP/S [12], the Tera Computer System [14], the Cray T-3D system [15], the Fujitsu AP-100 [17], the Parsytec GC [16], the PASM [18], and the Sanyo Edden/Cyberflow system [17].…”

mentioning

confidence: 99%

Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability

Sharma

Pradhan

1996

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

Computational sensors

Spiegel

1996

Intelligent Sensors

View full text Add to dashboard Cite

Helical latch for scalable Boolean logic operations

1994

View full text Add to dashboard Cite

Nanomechanical computing elements which employ rotational symmetry and motion are designed and analyzed using a bounded continuum model. First, the Boolean logic functions of NOT, AND, OR, and XOR are realized using a helical latch, reset springs, and rod assemblies. Building upon these components, designs for shifters and two-level logic devices are developed. The helical latching mechanism calculates the Boolean output function as a positional displacement from a known reset state, which occurs exactly once during each 360" instruction cycle. Operations of arbitrary word length can be performed by subdividing the logic disc into sectors where each sector operates on a single bit.Throughput can be increased by pipelining multiple-bit operands to yield a speedup which approaches a maximum value of (n + 2 ) as compared to a single-level of non-pipelined logic with n inputs. Generally, speedup is bounded by (n + 2 ) / p where p denotes the number of cycles between initiations of the pipe. An analysis of gate kinematics is performed to determine the device geometries and maximum operating frequencies for both non-pipelined and pipelined operation.

show abstract

Supercomputers-beyond today's supercomputers

Cited by 8 publications

References 0 publications

Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability

Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability

Computational sensors

Helical latch for scalable Boolean logic operations

Contact Info

Product

Resources

About