Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

Lee, R.T.-P.; Lim, Andy Eu-Jin; Tan, Kian-Ming; Liow, Tsung-Yang; Zhi, Dong; Yeo, Yee-Chia

doi:10.1109/led.2009.2017213

Cited by 86 publications

(11 citation statements)

References 10 publications

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“…In an alternative approach, the authors of [70] showed that deposition of an Al metal layer in vacuum using a Knudsen cell onto the air-exposed GaN surface caused interfacial reactions, resulting in the formation of oxide layers including Al 2 O 3 and Ga oxide at the interface. On p-type GaN, Lee et al have investigated two nanolaminate stacks composed of Al 2 O 3 /TiO 2 /Al 2 O 3 and MgO/TiO 2 /MgO [118,119] enabling a higher capacitance density while maintaining low gate leakage. They report that the best performance from both of these stacks is achieved when the GaN surface is treated with aqueous (NH 4 ) 2 S x , and a post metal anneal in N 2 .…”

Section: Gan Mosmentioning

confidence: 99%

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Long

McIntyre

2012

Materials

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The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

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Section: Gan Mosmentioning

confidence: 99%

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Long

McIntyre

2012

Materials

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“…It is found that the required switching electrical fields for SET and RESET of the CuI memristor are comparable to those of ECM memristors based on chalcogenides. [ 24,37–63 ] As these ECM memristors based on solid electrolyte (the area covered by the pink circle in Figure 1h) generally shows the lowest power consumption compared to their counterparts, the CuI memristor is promising for implementing low‐power in‐memory computing architecture. [ 26 ] At the same time, the fabrication processes for the reported ECM memristors are based on vacuum‐based deposition techniques.…”

Section: Resultsmentioning

confidence: 99%

Nonvolatile Logic‐in‐Memory Computing based on Solution‐Processed CuI Memristor

Wei

Luo

et al. 2022

Adv Elect Materials

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Memristors are intensively studied as being regarded as the critical components to realize the in‐memory computing paradigm. A novel electrochemical metallization memristor based on solution‐processed Pt/CuI/Cu structure is proposed and demonstrated in this work, with a high resistance switching ratio of 1.53 × 107. Owing to the efficient drift paths provided by Cu vacancies for Cu cations in CuI, very small operating voltages (Vset = 0.64 V and Vreset = −0.19 V) are characterized, contributing to ultralow standby power consumption of 9 fW and per set transition of 8.73 µW. Using CuI memristor arrays, a set of Boolean logic operations and a half‐adder are implemented. Moreover, by building the model for a 75 × 48 one‐transistor‐one‐memristor array, the feasibility of hardware encryption and decryption for images is verified. All these demonstrate that solution‐processed CuI memristors possess great potential in constructing energy‐efficient logic‐in‐memory computing architectures.

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“…The Hooge's parameter a H can give a measure of the total number of active traps which causing the noise and can be used as a rough figure of merit to characterize these devices. It can be expressed by the following equation [8][9][10] 11 respectively. In this work, the quality of the ZrO 2 /MgZnO interface directly determines the 1/f noise level and can therefore improve the traps of interface.…”

Section: Device Results and Discussionmentioning

confidence: 99%

Low Frequency Noise Analysis of Top-Gate MgZnO Thin-Film Transistor with High-κ ZrO2 Gate Insulator

Chiu

Lin

Chiu

et al. 2011

Electrochem. Solid-State Lett.

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In this work, depletion-mode magnesium doped zinc-oxide (MgZnO) channel thin film transistors (TFTs) with zirconium oxide (ZrO 2 ) gate insulator were fabricated using radio frequency magnetron sputtering deposition. Sputtered MgZnO TFT channel layer performed an average transmittance of 90% and an improved energy bandgap of 5.02 eV after 700 C post annealing. X-ray photoelectron spectroscopy (XPS) results indicated that the binding energy of Zn-O bonds and Mg-O bonds were enhanced following with the increasing of the post annealing temperatures. The low frequency noise spectra also indicated that the ZrO 2 /MgZnO was dominated by flicker noise and gate leakage induced noise was suppressed.Recently, ZnO and MgZnO attract considerable attention because they performed promising properties for short-wavelength optoelectronic and high breakdown voltage electronics devices due to their wide band gaps and large excitation binding energies. Compared to ZnO, MgZnO ternary alloy material provides several advantages, including continuously tunable bandgaps from 3.3 to 7.8 eV, which facilitated heterostructure with traditional ZnO-based material. 1-3 Magnesium atoms in MgZnO compound also exhibited slight lattice mismatch with ZnO because similar ionic radii between Mg 2þ and Zn 2þ . Moreover, Mg also acts as a donor, reducing the Madelung in MgZnO, and supporting the potential for development of p-type MgZnO thin films. For reasons concerning channel current density and breakdown voltage, the MgZnO channel TFT with a high energy bandgap and a high dielectric constant gate insulator is more promising compared to traditional Schottky gate contact TFT. In order to further enhance gate modulation ability of channel with the continuous scaling down of submicron thin-film transistors, the high-k dielectric insulator has become an essential issue owing to the strong demand for a low operating voltage and a low gate leakage current. Based on these considerations, ZrO 2 is a suitable candidate for gate dielectrics because ZrO 2 exhibited a large band gap (5.2-7.8 eV), a relatively high dielectric constant (>25), a high breakdown electric field (>5MV/cm) and an extreme high melting point (2750 C). 4 In addition, the ZrO 2 was deposited by electron beam evaporation at room temperature. Therefore, plasma induced surface damage and high-temperature high-k deposition processes can be avoided simultaneously because some specific substrates of TFT such as glass and polymer materials were extreme thermally sensitive. Figure 1 shows the cross sectional structure and top-view photography of top-gate MgZnO TFT with ZrO 2 gate insulator. The device gate length (L g ) and gate width (W g ) were 1 and 200 m, respectively. The MgZnO channel films used in this study were grown at room temperature by the RF sputtering method on c-face sapphire substrates. The MgZnO films were formed by a 6-inch ZnO/MgO (80/20 wt %) target. The channel thickness of the deposited MgZnO was 50 nm. After 1 minute post deposition annealing (PDA) at 700 C in an N 2 flow,...

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Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

Cited by 86 publications

References 10 publications

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Nonvolatile Logic‐in‐Memory Computing based on Solution‐Processed CuI Memristor

Low Frequency Noise Analysis of Top-Gate MgZnO Thin-Film Transistor with High-κ ZrO2 Gate Insulator

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