Subthreshold-current reduction circuits for multi-gigabit DRAM's

Low Power Memory Design

“…--... [20]. Part II impedance (Sw-Z) at the source of the N-MOSFET QN' consisting of a resistor Rs for limiting the subthreshold current and a switch Ss for bypassing Rs.…”

“…This scheme is also applicable to other logic gates as long as the input voltages are predictable. Another circuit for reducing the subthreshold current is to use a switched-power-supply inverter with a level holder [20], as shown in Figure 8.32(b). This is useful for some applications in which input voltage is not predictable as in the active mode of a DRAM, although there is a speed degradation due to QN' and Qp', and high-VTeventually restricts the lower limit of V DD' The power supply of the CMOS circuit is controlled by PET switches QN' and Qp'.…”

“…After one selected word line is activated, all the drivers are sources of subthreshold current, eventually dominating the total active current. The issue is overcome by partial activation of multi-divided power-line [20], as shown in Table 7. One-dimensional (ID) power-line selection features a selective power-supply to part of the Configuration Table 1 Partial activation of multi-divided power· line (22).…”

“…The subthreshold current is reduced, in inverse proportion to the number of sub-blocks, to (n/k)oj with an mok-fold reduction. In the conventional scheme, the active DC current is as high as 1.2 A for a hypothetically designed 16-Gb DRAM [20]. The dominant factor is the subthreshold current in the iterative circuit blocks such as word drivers, decoders, and SA driving circuits.…”

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

“…However, devices using advanced processes bring about large leakage currents due to increasing fabrication process fluctuations. To reduce these leakages, reverse-body bias schemes [1,2], and power-gating schemes [3,4,5,6] have been developed.…”