Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application

Abstract

A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus line and no other detection circuit is needed. Compared to traditional GGNMOS, with a 50 mm trigger PMOS, the trigger voltage of the single finger structure can be reduced from 7.15 to 4.97 V and it also has lower overshoot voltage. Also the ultrathin gate oxide can be effectively protected, which is very important in nanometre circuits. For the multi-finger structure, with a 30 mm trigger PMOS the proposed structure showed a 15.9% reduction in trigger voltage and a 13.5% increment as to failure current compared to traditional GGNMOS.

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

“…In a Bipolar-CMOS-DMOS (BCD) process, high voltage (HV) DMOS, low voltage (LV) CMOS and bipolar devices can be integrated on one single chip. In the LV domain, the GGNMOS has been frequently used for ESD protection because of its simple structure and superior intrinsic ESD performance [1]. However, it can suffer from non-uniform turn-on across multiple device fingers, reducing its robustness.…”

A novel SCR structure integrated with power clamp for ESD protection at I/O pad

“…Though it has good compatibility with CMOS process, its inhomogeneous turning on characteristic can lead to low ESD robustness [3]. Besides, its large parasitic capacitance can degenerate the frequency characteristic in high frequency circuits.…”

Study of current saturation behaviors in dual direction SCR for ESD applications

“…Electrostatic discharge (ESD) has been one of the most important and challenge issues in the CMOS integrated circuits as the processing advances [1,2]. Traditional ESD protection structures, like Grounded-Gate NMOS (GGNMOS) and SCR, provide forward direction protection and rely on the body diode to shunt ESD current at backward direction.…”

“…In order to provide dual direction protection, DDSCR, as one of the most area efficient ESD devices [3], is successfully devised and applied for on-chip-ESD protection [3][4][5][6]. The earlier publications mainly focused on reducing the trigger voltage, analyzing and improving ESD robustness and minimizing latch-up risks [1][2][3][4], however, current saturation behavior has great effect on its ESD performance in terms of effectiveness and robustness. In this paper, the current saturation behavior in DDSCR and NMDDSCR under transmission line pulse (TLP) stress is investigated and analyzed.…”