Substrate RF Losses and Non-linearities in GaN-on-Si HEMT Technology

Short-channel Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) often utilize T-shape gates due to their large gate-line cross-sectional area and subsequent fMAX increase. In this paper, we report the linearity trade-offs associated with varying the T-gate geometries of AlGaN/GaN HEMTs on Si, specifically the gate extensions which serve as field plates and their impact on the large-signal performance. Small-signal characterization and modeling, in addition to TCAD, provide initial guidelines for the optimal dimensions for the gate field plates using the ratio of fT and the product of the gate resistance and the gate-to-drain capacitance. We utilize various characterization methods, including 6 GHz non-linear vector network analyzer characterization in addition to load-pull, to quantify the amplitude and phase distortion and their subsequent impact on the large-signal metrics of the devices under differing matching conditions and bias points. We deduce that the influence of the gate field plates on the amplitude and phase distortion is non-negligible, particularly under matched conditions.

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“…4) [13,14]. The work in [15,16] provides further insight into the substrate-related RF losses and nonlinearities for these GaN HEMTs on Si.…”

Section: The Gan Hemt Devicesmentioning

confidence: 99%

RF linearity trade-offs for varying T-gate geometries of GaN HEMTs on Si

ElKashlan

Khaled

Rodríguez

et al. 2023

Int. J. Microw. Wireless Technol.

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“…The implant consists of 3 steps of increasing energy (75, 150 and 375 keV). It is suggested by TRIM simulations that N-induced defects are not found at depth greater than ~600 nm from channel surface [7], [14].…”

Section: A Substrate Fabrication and Processingmentioning

confidence: 99%

“…Second (H2) and third (H3) harmonic power are measured at the end of the CPW line. In order to correct for the varying RF loss along the line, H2 and H3 are interpolated at an output first harmonic power (the fundamental H1) of 15 dBm which is a commonly used power level for reporting substrate-induced distortion [7], [10]. The noise floor of the HD setup is ~-110 dBm.…”

Section: B Measurement Techniquesmentioning

confidence: 99%

“…For GaN-on-high resistivity (HR) Si wafer, it is commonly accepted that RF losses are dominated by a parasitic surface conduction (PSC) layer which forms close to Si top surface [4], [5], [6], [7]. The PSC layer is mainly formed by diffusion of Al and Ga atoms into the first 1-2 micrometres of the Si substrate during high thermal budget epitaxy of the III-N layers.…”

Section: Introductionmentioning

confidence: 99%

“…A lower ρeff can lead to increased crosstalk and harmonic distortion (HD) [3], [9]. As demonstrated in [6], [7], by carefully engineering the III-N buffer and AlN nucleation layers, it is possible to recover high values of ρeff with low levels of distortion, comparable to stateof-the art "trap-rich" Silicon-on-Insulator (SOI) substrates [10].…”

Section: Introductionmentioning

confidence: 99%

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Effect of Buffer Charge Redistribution on RF Losses and Harmonic Distortion in GaN-on-Si Substrates

Cardinael,

Yadav,

Parvais

et al. 2024

IEEE J. Electron Devices Soc.

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Understanding and mitigation of substrate RF losses and signal distortion are critical to enable highperformance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity (𝝆 𝒆𝒇𝒇 ) in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the 𝝆 𝒆𝒇𝒇 degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in 𝝆 𝒆𝒇𝒇 at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of 2 nd harmonic power of up to 5 dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaNon-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (VFB) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.

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