Substrate removal and BOX thinning effects on total dose response of FDSOI NMOSFET

Section: B Devicesmentioning

confidence: 99%

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Gaillardin

Girard

Paillet

et al. 2013

“…The nFET drive strength increases while the pFET drive strength decreases with an increase in wafer bias. This is because the BOX/SOI interface is capacitively coupled to the front thin-oxide/SOI interface [11]. The change in transistor drive current observed at positive substrate bias voltages is analogous to the effect of the positive charge induced by ionizing radiation and trapped in the BOX [12].…”

Section: Discussionmentioning

confidence: 99%

“…During irradiation, the circuit was biased so that VDD was at 1.5 V, ground at 0 V and the input of the inverter chain was at 0 V. In this condition, every other CMOS inverter has an nFET and a pFET that is off state. Ionizing radiation effects are worst for this bias condition for this FDSOI technology [11].…”

Section: Experiments Descriptionmentioning

confidence: 96%

Effects of Ionizing Radiation on Digital Single Event Transients in a 180-nm Fully Depleted SOI Process

Gouker

Gadlage

McMorrow

et al. 2009

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts in FET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.

“…Synergy between radiation and electrical stresses happens because of the presence of physically damaged regions left by irradiation, as we proposed in the case of bulk CMOS [6]. In parallel, radiation damage on deep-submicron SOI devices Manuscript with ultra-thin gate oxides has been recently investigated after X-ray [7], [8] and proton exposure [9]- [11]. Yet, the reaction of irradiated SOI devices fabricated in a contemporary CMOS technology to subsequent accelerated electrical stresses is still a virgin chapter in the radiation effects field, at least concerning high LET particles.…”

Section: Introductionmentioning

confidence: 99%

Electrical stresses on ultra-thin gate oxide SOI MOSFETs after irradiation

Cester

Gerardin

Paccagnella

et al. 2005

We present the first experimental data about the wear-out of a 0.1 m partially depleted SOI CMOS technology after heavy ion irradiation. We show that accelerated life tests based on high electric fields yield significant differences between irradiated and nonirradiated devices, even though no or only minor changes are visible in the characteristics of the devices after irradiation. First, the time to breakdown of the front gate oxide is significantly lower in the irradiated samples. The fresh devices experienced breakdown after 5-8 10 22 electrons/cm 2 were injected across the oxide during high field electrical stress. In the irradiated oxide, the breakdown was reached at much lower injected charge values, between 0 5 10 22 electrons/cm 2 and 1 5-1 10 22 electrons/cm 2 depending on the ion fluences. This translates into a lifetime reduction of 10%-20% of its initial value. Furthermore, the degradation kinetics of the threshold voltage and transconductance peak are strongly affected by ion strikes. In particular, a sudden shift of the threshold voltage and an acceleration in the degradation of the transconductance peak were observed upon the application of an electrical stress, which have no correspondence in nonirradiated devices. An acceleration in the degradation of the parasitic back transistor was observed as well. These phenomena were interpreted in terms of latent damage left by the irradiation in the oxides that make up SOI devices.Index Terms-CMOS devices and integrated circuits reliability, gate oxide reliability, radiation effects on MOSFETs, silicon on insulator.