Substrate noise simulation for high frequency CMOS system on chip design

Gavriilidou, V.; Noulis, Thomas; Siskos, S.

doi:10.1109/mocast.2016.7495129

Cited by 1 publication

(1 citation statement)

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“…The digital block consists of 40 gate families and each gate separately includes 2200 CMOS logic standard cells. To minimize the complexity of the digital block, a chain of inverters were chosen for the digital circuit [20]. The supply voltage is 1.2 V and the clock frequency 100 MHz.…”

Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%

System on Chip Noise Integrity Simulation

Gavriilidou

Voulkidou

Noulis

et al. 2022

Chips

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In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

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Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%