Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Komatsu, Yoshihide; Ishibashi, Koji; Nagata, Makoto

doi:10.1093/ietele/e90-c.4.692

Cited by 1 publication

(2 citation statements)

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“…On the other hand, the LVth cell can increase the failure tolerance more than that for HVth in the range of a higher z-score, because lowering Vth with a lower dopant concentration leads to smaller σVth, resulting in a smaller variation of SNM (σSNM). The σVth is expressed as equation (2), where φ bi is the Fermi level, V bs is the body bias, ε Si is the dielectric constant of silicon, ε ox is the dielectric constant of oxide, q is the unit charge, Na is the doping concentration, Tox is the oxide thickness of MOSFET and Leff and Weff are the length and width of the transistor, respectively [2]. (2) The σVth can be reduced by lowering the Na [3].…”

Section: Reducing Mismatch Of Cell-margin Characteristicsmentioning

confidence: 99%

“…Since Vth and σVth are reduced by decreasing the dopant concentration [2][3][4], the Vth mismatch in the high z-score range can be reduced by the proposed LVth cell, compared with the commonly-used conventional higher Vth (HVth) cell. The mismatch of the cell-margin characteristics is alleviated with the proposed LVth cell, and the failure probability at an actually-required higher z-score point is reduced.…”

Section: Introductionmentioning

confidence: 99%

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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

Yamauchi

2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (σVth) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to 6σ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

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Section: Reducing Mismatch Of Cell-margin Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%