Subnanosecond Fluctuations in Low-Barrier Nanomagnets

Kaiser, Jan; Rustagi, Avinash; Çamsarı, Kerem Y.; Sun, J. Z.; Datta, Supriyo; Upadhyaya, Pramey

doi:10.1103/physrevapplied.12.054056

Cited by 40 publications

(37 citation statements)

References 51 publications

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“…The Arrhenius law which describes the thermal fluctuations of high barrier magnets (∆ k B T ) with two distinct magnetic states thus does not hold for LBM [17], [27]. Instead, thermal fluctuations in monodomain low barrier magnets could be characterized starting from Fokker-Planck equation (FPE) [28], [29] or the Landau-Lifshitz-Gilbert (LLG) equation including a Langevin term describing thermal fluctuation [27], [30].…”

Section: Low Barrier Magnetsmentioning

confidence: 99%

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

et al. 2019

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Binary stochastic neurons (BSN's) form an integral part of many machine learning algorithms, motivating the development of hardware accelerators for this complex function. It has been recognized that hardware BSN's can be implemented using low barrier magnets (LBM's) by minimally modifying presentday magnetoresistive random access memory (MRAM) devices. A crucial parameter that determines the response of these LBM based BSN designs is the correlation time of magnetization, τc. In this letter, we show that for magnets with low energy barriers (∆ ≈ kBT and below), circular disk magnets with inplane magnetic anisotropy (IMA) lead to τc values that are two orders of magnitude smaller compared to τc for magnets having perpendicular magnetic anisotropy (PMA) and provide analytical descriptions. We show that this striking difference in τc is due to a precession-like fluctuation mechanism that is enabled by the large demagnetization field in IMA magnets. We provide a detailed energy-delay performance evaluation of previously proposed BSN designs based on Spin-Orbit-Torque (SOT) MRAM and Spin-Transfer-Torque (STT) MRAM employing low barrier circular IMA magnets by SPICE simulations. The designs exhibit sub-ns response times leading to energy requirements of ∼a few fJ to evaluate the BSN function, orders of magnitude lower than digital CMOS implementations with a much larger footprint. While modern MRAM technology is based on PMA magnets, results in this paper suggest that low barrier circular IMA magnets may be more suitable for this application.Index Terms-Binary stochastic neuron, hardware implementation, low barrier magnet, embedded MTJ, probabilistic computing

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Section: Low Barrier Magnetsmentioning

confidence: 99%

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

et al. 2019

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“…The fluctuation rates are highly sensitive to applied fields and currents. The two state fluctuator model used in this paper is not valid for fluctuator frequencies approaching the 10 −9 s time scale of magnetization reversal [39], but for applications like ours in which a reference resistor is present, Kaiser et al [40] show that frequency scales can exceed the 1 GHz regime. The achievable time scale depends on the differences in the resistance, proportional to the tunneling magnetoresistance of the magnetic junction, that can be detected and the size of the current needed to do so.…”

Section: Precharge Sense Amplifier Readout Of Superparamagnetic Tmentioning

confidence: 87%

“…[18] makes similar order of magnitude energy projections as ours in the case that the SMTJ dwell time could be reduced to ≈ 1 ns. Theory [40] suggests that nanomagnets with autocorrelation times on this scale might be realizable in the limit that the barrier goes to zero. Realizing devices that operate in this regime face a number of obstacles.…”

Section: Appendix C: Comparison With P-bitsmentioning

confidence: 99%

Energy-Efficient Stochastic Computing with Superparamagnetic Tunnel Junctions

et al. 2020

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Superparamagnetic tunnel junctions have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers which is more energy efficient than previously explored alternatives. The energy savings offered by this digital generator survive when we use them as the fundamental units of a neural network architecture. To take advantage of the potential savings, we codesign the algorithm with the circuit, rather than directly transcribing a classical neural network into hardware. The flexibility of the neural network mathematics compensates for explicitly energy efficient choices we make at the device level. The result is a convolutional neural network design operating at ≈ 150 nJ per inference with 97 % performance on MNIST-nearly an order of magnitude more energy efficiency than comparable proposals in the recent literature. * matthew.daniels@nist.gov † mark.stiles@nist.govThe low energy, truly random behavior, ease of control, and established compatibility with complementarymetal-oxide-semiconductor (CMOS) circuitry has led to the use of SMTJs as the basis for a number of novel computing schemes [11][12][13]. SMTJs were proposed to implement the concept of probabilistic bits, or "p-bits," which were leveraged for applications as Bayesian neural networks [14][15][16], invertible Boolean logic [17,18], reservoir computing [19], and Ising network models applied to optimization problems [20,21]. SMTJs were also proposed as stochastic neural units [22] that can interact with synaptic units, emulated by crossbar arrays of mag-

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“…Due to the fast thermal fluctuations of the LBM in the MTJ, Eq. (1) can be evaluated on a subnanosecond timescale leading to fast generation of samples 19,20 . Fig.…”

Section: Clockless Learning Circuit Emulating Eqs(1)-(3)mentioning

confidence: 99%

Probabilistic Circuits for Autonomous Learning: A Simulation Study

Kaiser

Faria

Datta

2020

Front. Comput. Neurosci.

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Modern machine learning is based on powerful algorithms running on digital computing platforms and there is great interest in accelerating the learning process and making it more energy efficient. In this paper we present a fully autonomous probabilistic circuit for fast and efficient learning that makes no use of digital computing. Specifically we use SPICE simulations to demonstrate a clockless autonomous circuit where the required synaptic weights are read out in the form of analog voltages. Such autonomous circuits could be particularly of interest as standalone learning devices in the context of mobile and edge computing.

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Subnanosecond Fluctuations in Low-Barrier Nanomagnets

Cited by 40 publications

References 51 publications

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

Energy-Efficient Stochastic Computing with Superparamagnetic Tunnel Junctions

Probabilistic Circuits for Autonomous Learning: A Simulation Study

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