Sub-sampling band-pass-Sigma-Delta modulator for baseband processing

Abstract

Personal mobile communication devices have seen tremendous growth the last few years. Increasing demands for broadband multimedia applications have been witnessed. However present-day architectures, standards are not suited for these applications. The narrow channel bandwidths pose a technical bottleneck in increasing the data rates. Third Generation (3G) wireless systems are being defined specifically for these applications. Moreover recent trends in Radio Frequency (RF) transceiver design focus on low-cost, low-power, small form factor, programmable devices. There is also a special emphasis on programmability and compatibility to different communication standards. For these objectives, the Direct Conversion Receiver (DCR) seems to be the ideal choice. Such a system would employ a wide-band Analog to Digital Converter (ADC) that can both digitize the desired channel and reject adjacent channel interferers. Sigma-Delta (SD) ADCs are best suited for these functions. SD ADCs achieve this by using oversampling combined with noise shaping. The decimation filter can further suppress both the quantization noise and interferers. Since SD ADCs trade off analog circuit complexity for increased digital processing, these architectures would be more power-efficient. In this thesis, a "pseudo" band-pass (sub-sampling) Sigma-Delta modulator is designed for use in the baseband section of a RF transceiver for wide-band CDMA system. This modulator down-converts the incoming RF signals to baseband and then digitizes them. A prototype is developed and fabricated in TSMC 0.25µ digital CMOS process. This is then tested and its performance compared with the simulation results. Measurements indicate that the prototype meets the performance requirements.