Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2020

Self Cite

The growing need for connected, smart and energy efficient devices requires them to provide both ultra-low standby power and relatively high computing capabilities when awoken. In this context, emerging resistive memory technologies (RRAM) appear as a promising solution as they enable cheap fine grain technology co-integration with CMOS, fast switching and non-volatile storage. However, RRAM technologies suffer from fundamental flaws such as a strong device-to-device and cycle-to-cycle variability which is worsened by aging, forcing the designers to consider worst case design conditions. In this work, we propose, for the first time, a circuit that can take advantage of recently published Write Termination (WT) circuits from both the energy and performances point of view. The proposed RRAM Variability Aware Controller (RRAM-VAC) stores and then coalesces the write requests from the processor before triggering the actual write process. By doing so, it averages the RRAM variability and enables the system to run at the memory programming time distribution mean rather than the worst case tail. We explore the design space of the proposed solution for various RRAM variability specifications, benchmark the effect of the proposed memory controller with real application memory traces and show (for the considered RRAM technology specifications) 44 % to 50 % performances improvement and from 10% to 85% energy gains depending on the application memory access patterns.

Section: Write Termination Circuitsmentioning

confidence: 99%

Section: Write Termination Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Tuli

Rios

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2020

Self Cite

“…OxRAM switching times (i.e. tForming, tSET and tRESET) show wide distributions [23]. To guarantee successful programming of all memory cells in OxRAM array, one pulse programming approach is used.…”

Section: B Oxram Modelmentioning

confidence: 99%

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

Alayan

Muhr

IEEE Trans. Circuits Syst. II

et al. 2019

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of memory elements (e.g. pulse widths and amplitudes) must cover the tail bits to avoid programming failures. Switching time of ReRAMs shows wide distributions. Therefore, fast cells are subjects for electrical stress after their switching and energy waste since programming currents are typically large for this technology (tens of µA). In this paper, we present a Write Termination (WT) circuit to stop the programming operation when the switching event occurs in the selected memory element. The proposed design is sensitive to current variations that take place when the memory element switches between two different resistance states (LRS and HRS). This WT scheme reduces the power consumption by 97+%, 93+% and 65+% during Forming, RESET and SET operations respectively. Our estimations show that area efficiency of 70% for a memory array is achievable when the presented WT circuit is integrated in near-memory peripheries. The demonstrated WT circuit is suitable for different ReRAM technologies with small overhead penalty and shows robustness against CMOS and ReRAM variabilities.

“…While it has been shown that the time distribution can strongly move with cycle to cycle or device to device variability, we assume that a smart circuit such as [29] is considered. This way, it enables reliable write operation while limiting the programming time.…”

Section: Crosspoint Positionningmentioning

confidence: 99%

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

Giraud

Noël

et al. 2018

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resistive Switching Technologies (RRAM) proposes a potential solution to this demand for fast, low cost, high density and non-volatile memory. However, nowadays transistorless RRAM-based architectures, such as Crosspoint, suffers of several issues such as sneakpath, IRdrop and periphery overhead. In this work, we propose to explore the positioning of RRAM crosspoint memories regarding DRAM and NAND in terms of density and write throughput. We present several design guidelines then show that for the optimal RRAM crosspoint architecture (2-layers with common bitline), massively multiple bank write is the solution to optimize density and write throughput to around 20-100Gbit/cm2 and 200-500MB/s respectively for 32 to 64 parallel access.