Sub‐harmonic upconversion mixer using 0.18 μm CMOS technology

Abstract

A novel sub-harmonic upconversion mixer using Chartered 0.18 μm radio-frequency (RF) CMOS technology for 2.4 GHz wireless application is introduced. Using the sub-harmonic technique, the required local oscillator (LO) frequency can be reduced a half, which simplifies the design of the LO. Moreover, the sub-harmonic technique can effectively reduce the influence of LO leakage. The measured results demonstrate that the novel upconversion mixer can provide about 14.4 dB conversion gain, whereas the power consumption is only 1.65 mW with a 1 V supply voltage, and the input-referred thirdorder intercept point (IIP3) of the mixer is about 4 dBm. The chip area including test pads is only 0.7 × 0.72 mm 2 .

Advances on intelligent algorithms for scientific computing: an overview

“…In Chen et al (2013), a folded up-conversion mixer was proposed by the authors, which employs a current reuse technique and achieves a conversion gain of 9.5 dB at a 1 V supply voltage while consuming only 258 µW of power. In Jin et al (2014b), the authors presented a sub-harmonic up-conversion mixer that halves the required local oscillator frequency and achieves a higher conversion gain of 14.4 dB, albeit at the cost of increased power consumption of 1.65 mW at 1 V supply voltage. In Jin and Yu (2013), a current-reuse current-mirror-switch mixer was investigated by the authors, which features 8.5 dB conversion gain, 1.16 mW power consumption, lower supply voltage, higher linearity, and smaller chip area.…”