Sub-60 nm physical gate length SOI CMOS

Yang, Insoon; Chen, K.; Smeys, P.; Sleight, J.W.; Lin, Li-Te; Leong, M.; Nowak, E.; Fung, S.K.H.; Maciejewski, E.; Varekamp, P.; Chu, Wei‐Min; Park, H.; Agnello, P.; Crowder, S.; Assaderaghi, F.; Su, Li

doi:10.1109/iedm.1999.824186

Cited by 7 publications

(3 citation statements)

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“…From the point of view of scale length, this would seem advantageous because like the 170 C case, it would reduce the depletion depth, which would enable further scaling. Another effect is that the forward body bias may be strongly dependent on the drain voltage, potentially causing large output conductance such as that seen recently in 52-nm physical gate length PD-SOI [96]. If is increased on the DG-FET designs, the same sort of effect would be expected.…”

Section: Discussionmentioning

confidence: 83%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Section: Discussionmentioning

confidence: 83%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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“…In order to reproduce the entire Vt characteristic however, it may be necessary for some amount of boron deactivation to take place at the surface as well. Carbon implant was added to an SOI device processed similarly to the conditions reported by Yang et al [4].…”

Section: Device Resultsmentioning

confidence: 99%

Carbon Implanted Halo for Super Halo Characteristic NFETs in Bulk and SOI

Ellis-Monaghan

Lee

Ieong

et al. 2001

31st European Solid-State Device Research Conference

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For high performance deep sub .08um CMOS technologies, minimizing short channel effect (SCE) can result in significant improvements in nominal device performance. We show that with carefully chosen carbon implants in the NFET extension and halo region, superior halo performance is achievable. This "Super Halo" characteristic[1], results in an improvement in SCE and a subsequent improvement in Idsat. The carbon implants are placed to reduce the transient diffusion of the boron halo (TED) while not extending deep enough to become a dominant source of leakage. The net is an improved device characteristic resulting in an equivalent performance gain of 80uA/um at nominal with the same Ioff at minimum for both bulk CMOS and SOI technologies.

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“…This was not a concern for large features, but for future generations the actual linewidth approaches this offset. Recent papers show that the final gate CDs for the 130nm technology node will be between 50nm and 80nm to fabricate higher speed devices [3][4] . We need to reduce the bias between SEM and electrical linewidth measurements in order to extend the electrical measurement technique.…”

Section: Introductionmentioning

confidence: 99%

Electrical linewidth measurement for next-generation lithography

Kye

Levinson

2001

SPIE Proceedings

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In recent years electrical linewidth measurement (ELM) has become accepted as an efficient method to gather large amounts of linewidth data rapidly and accurately. However, there are offsets between electrical and SEM measurements. While these have not been a concern for large features, it is important to minimize the bias as the actual linewidth approaches the offset. The purpose of this paper is to demonstrate that ELM can be used to measure linewidths much smaller than 100nm. Our experiments show that out-diffusion and surface ion depletion are the primary sources of bias in electrical linewidth measurement. Silicon nitride capping layers before annealing are helpful to prevent out-diffusion.

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Sub-60 nm physical gate length SOI CMOS

Cited by 7 publications

References 0 publications

Device scaling limits of Si MOSFETs and their application dependencies

Device scaling limits of Si MOSFETs and their application dependencies

Carbon Implanted Halo for Super Halo Characteristic NFETs in Bulk and SOI

Electrical linewidth measurement for next-generation lithography

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