Sub-50 mV power supply, recursive stacking body bias NAND gate for extremely low-voltage CMOS LSIs

Abstract

This paper presents a recursive stacking body-bias NAND for extremely low voltage application. Our proposed NAND utilizes recursive-stacking and body-bias techniques to achieve extremely low-voltage operation. The former suppresses off-leakage current of MOSFETs and enhances the voltage gain of the NAND gate. The latter achieves on-current enhancement and the voltage gain improvement of the NAND gate. Performance improvements of our proposed NAND gate are theoretically analyzed and discussed. Simulation of our proposed NAND gates showed that voltage transfer curves, voltage gains, and voltage swings were improved significantly. A prototype chip was fabricated in a 180 nm CMOS process and demonstrated that the voltage swing of the proposed NAND was 44.1 mV at 50 mV power supply, which was 16.4 mV improvement compared to that of the standard NAND gate, at the cost of area, power, and delay time.