Sub-20-nm Alignment in Nanoimprint Lithography Using Moiré Fringe

Abstract

Accurate multi-level overlay capability for nanoimprint lithography (NIL) is essential to integrated circuit manufacturing and other multilayer imprint applications. Using the "beat" grating image (Moiré fringe) generated by overlaying two sets of gratings that have slightly different periods, we obtained an alignment signal with a sensitivity better than 10 nm in nanoimprint lithography. The alignment signal is, as expected, independent of the size of the gap between the wafer and the imprint mold. We achieved a single-point overlay accuracy (error distribution) of sub-20 nm between the first and second imprinted layers by using two sets of Moiré fringes. With higher precision nanopositioning stages, better single-point alignment accuracy is expected. Furthermore, we achieved sub-150 nm alignment over an area of 1 sq in and sub-250 nm over the entire area of a 4 in wafer using simple low-resolution stages without temperature control or wafer-mold mismatch compensation. With better stages, precision temperature control, and wafer-mold mismatch compensation, we believe that much higher overlay alignment accuracy over large areas (either in a 1 sq in die or a full wafer) is feasible.

Sandwich-typed resonator cavity based on a regular photonic crystal nanobeam

“…The misalignment offset of the ellipse, in the direction perpendicular to the axis of the waveguide, is most critical. Modern technologies allow combining structural layers within ~10 nm error [15]. Figure 4 shows that when the transverse displacement is only 20 nm, the Q-factor does not exceed 10 3 for A=4.08 um.…”

Two-component nanocavity based on a regular photonic crystal nanobeam

“…При этом погрешность смещения эллипса в направлении перпендикулярном оси волновода наиболее критична. Современные тех-нологии позволяют совмещать структурные слои с точностью ~10 нм [15]. Из рис.…”

Nanoimprint Lithography

“…Furthermore, they achieved sub-150 nm alignment over an area of 1 sq in and sub-250 nm over the entire area of a 4 in wafer using simple low-resolution stages without temperature control or wafer-mold mismatch compensation. With better stages, precision temperature control, and wafer-mold mismatch compensation, they believe that much higher overlay alignment accuracy over large areas (either in a 1 sq in die or a full wafer) is feasible (Li et al, 2006). Pan and Chen developed a self-built multilayer aligner for multilayer-imprint process to fabricate thin film transistor-liquid crystal display (TFT-LCD).…”