Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length

Pitner, Gregory; Zhang, Z.; Lin, Qing; Su, Sheng-Kai; Gilardi, Carlo; Kuo, Chihping; Kashyap, Harshil; Weiß, Tilo; Yu, Zhouchangwan; Chao, Tsu-Ang; Li, L.-J.; Mitra, Subhasish; Wong, H.-S. Philip; Cai, Jin; Kummel, Andrew C.; Bandaru, Prabhakar R.; Passlack, M.

doi:10.1109/iedm13553.2020.9371899

Cited by 18 publications

(17 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, the bottom-gate device geometry can be replaced by a dual-gate or a gate-all-around geometry to further improve the gate coupling efficiency and to enable the further downscaling of GNR transistors [44,46,47].…”

Section: J O U R N a L P R E -P R O O Fmentioning

confidence: 99%

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Lin

Barin

Hong

et al. 2023

Carbon

View full text Add to dashboard Cite

Section: J O U R N a L P R E -P R O O Fmentioning

confidence: 99%

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Lin

Barin

Hong

et al. 2023

Carbon

View full text Add to dashboard Cite

Section: Resultsmentioning

confidence: 95%

“…Use of Si and SiGe FinFETs may be challenging at these dimensions due to their low carrier mobility (<100 cm 2 /V s) and difficulties in strain engineering in nanowire geometries. , However, carbon nanotubes (CNTs) have higher mobility, exceeding 3000 cm 2 /V-s, , and are less susceptible than Si/SiGe FinFETs to short-channel effects due to the ∼1 nm body thickness. The increased mobility enables drive currents in excess 10 μA/CNT, while the band gap (∼0.8 eV/ d t , where d t is the CNT diameter) enables an on/off switching ratio exceeding five orders of magnitude . There have also been reports of sub-threshold swings possibly less than 59 mV/decade, from tunneling assisted processes in CNT-based devices. ,,− …”

Section: Introductionmentioning

confidence: 99%

“…In the present report, it is shown that ALD may be optimized for high quality and conformal gate oxide deposition with precise control of the layer thickness on CNTs. It was previously reported that aluminum oxide (Al 2 O 3 ) could be deposited conformally on top of HOPG surfaces by a low-temperature ALD process without any seeding layers and surface pretreatment. , The related principles for producing a pinhole-free, sub-2 nm Al 2 O 3 film are first extended on HOPG to investigate the film nucleation mechanism during the first several deposition cycles. By tuning the precursor pulse, purge time, and the substrate temperature, sub-nanometer low-temperature AlO x (LT AlO x ) particles are formed which nucleate on the HOPG surface.…”

Section: Introductionmentioning

confidence: 99%

“…The increased mobility enables drive currents in excess 10 μA/CNT, while the band gap (∼0.8 eV/d t , where d t is the CNT diameter) enables an on/off switching ratio exceeding five orders of magnitude. 6 There have also been reports of sub-threshold swings possibly less than 59 mV/ decade, from tunneling assisted processes in CNT-based devices. 2,5,7−11 A major problem in the fabrication of single CNT-based field-effect transistors (FETs) has been the growth of a high dielectric constant (high-k) gate oxide on CNT channels.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth

Zhang

Passlack

Pitner

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to date, the lack of dangling bonds on sp 2 oriented graphene sheets has limited the high precursor nucleation density enabling atomic layer deposition of sub-1 nm EOT gate oxides. It is shown here that by deploying a low-temperature AlO x (LT AlO x ) process, involving atomic layer deposition (ALD) of Al 2 O 3 at 50 °C with a chemical vapor deposition (CVD) component, a high nucleation density layer can be formed, which templates the growth of a high-k dielectric, such as HfO 2 . Atomic force microscopy (AFM) imaging shows that at 50 °C, the Al 2 O 3 spontaneously forms a pinhole-free, sub-2 nm layer on graphene. Density functional theory (DFT) based simulations indicate that the spreading out of AlO x clusters on the carbon surface enables conformal oxide deposition. Device applications of the LT AlO x deposition scheme were investigated through electrical measurements on metal oxide semiconductor capacitors (MOSCAPs) with Al 2 O 3 /HfO 2 bilayer gate oxides using both standard Ti/ Pt metal gates as well as TiN/Ti/Pd gettering gates. In this study, LT AlO x was used to nucleate HfO 2 and it was shown that bilayer gate oxide stacks of 2.85 and 3.15 nm were able to achieve continuous coverage on carbon nanotubes (CNTs). The robustness of the bilayer was tested through deployment in a CNT-based field-effect transistor (FET) configuration with a gate leakage of less than 10 −8 A/μm per CNT.

show abstract

Small Molecule Additives to Suppress Bundling in Dimensional‐Limited Self‐Alignment Method for High‐Density Aligned Carbon Nanotube Array

Chao,

Chuu,

Liew

et al. 2023

Adv Materials Inter

View full text Add to dashboard Cite

Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when utilizing the state‐of‐the‐art dimension‐limited self‐alignment (DLSA) method, poses challenges. These CNT bundles degrade the transistor gate's efficiency in controlling the flow of charge carriers in the CNT channel, leading to pronounced device‐to‐device variability. Here, a novel method is introduced to alleviate bundling in CNT arrays assembled via DLSA, by involving small molecule additive to screen the attractive van der Waals force between neighboring CNTs during the DLSA process, resulting in over 50% reduction in CNT bundling. Furthermore, a pioneering methodology for quantifying CNT bundles is presented and employed experimentally to assess bundles in dense CNT arrays assembled by DLSA using transmission electron microscopy. Both experimental data and molecular dynamics simulation reveal that CNT bundling originates from van der Waals attraction between CNTs, and the disturbed liquid‐liquid interface by accumulating excess polar molecules. These findings illuminate new pathways for realizing dense, bundle‐free CNT arrays.

show abstract

Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length

Cited by 18 publications

References 11 publications

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth

Small Molecule Additives to Suppress Bundling in Dimensional‐Limited Self‐Alignment Method for High‐Density Aligned Carbon Nanotube Array

Contact Info

Product

Resources

About