Study on gate‐source voltage oscillation suppression in SiC MOSFETs based on LCR parallel branch

Abstract

Silicon carbide (SiC) MOSFETs are garnering widespread attention due to their superior performance in high‐temperature, high‐frequency, and high‐voltage applications, emerging as the preferred power semiconductor devices in converters for photovoltaic power generation and new energy vehicles. However, SiC MOSFETs are prone to gate drive and drain‐source voltage oscillations during high‐speed switching events, resulting in diminished system efficiency, increased electromagnetic interference, reduced device safety, and even compromising the overall reliability of the converter. This paper introduces an oscillation suppression method based on a gate LCR parallel branch, aimed at optimizing the switching performance of SiC MOSFETs. A half‐bridge circuit model based on SiC MOSFET is established, and the mechanism of gate and drain‐source oscillation is meticulously analysed using the transfer function expression. Building upon this, the LCR parallel branch parameters are meticulously designed to introduce appropriate damping in the gate drive path, effectively mitigating oscillations. Experimental results demonstrate that the proposed design not only significantly reduces the amplitude of oscillations but also shortens the switch‐transition time. This enhancement effectively increases the switching frequency and reduces switching losses.