Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions

Possémé, N.; David, T.; Chevolleau, T.; Darnon, Maxime; Bailly, F.; Bouyssou, R.; Ducoté, J.; Chaabouni, H.; Kodadi, Mohamed El; Licitra, C.; Verove, C.; Joubert, O.

doi:10.1149/1.3572312

Cited by 4 publications

(2 citation statements)

References 40 publications

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“…In this paper, we study the etching process of low-k material, which is the first step in the so-called 'Damascene' process, describing the production of Cu interconnects [3]. In the literature, several experimental papers about the Damascene process and about dry etch challenges of low-k materials in general have been published [4][5][6][7][8][9][10][11][12][13]. Most papers on this topic report on the etching of dense and porous SiCOH (i.e.…”

Section: Introductionmentioning

confidence: 99%

Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation

Laer

Tinck

Šamara

et al. 2013

Plasma Sources Sci. Technol.

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In this paper, we investigate the etch process of so-called low-k organic material by means of a N 2 /H 2 capacitively coupled plasma, as applied in the micro-electronics industry for the manufacturing of computer chips. In recent years, such an organic material has emerged as a possible alternative for replacing bulk SiO 2 as a dielectric material in the back-end-of-line, because of the smaller parasitic capacity between adjacent conducting lines, and thus a faster propagation of the electrical signals throughout the chip. Numerical simulations with a hybrid plasma model, using an extensive plasma and surface chemistry set, as well as experiments are performed, focusing on the plasma properties as well as the actual etching process, to obtain a better insight into the underlying mechanisms. Furthermore, the effects of gas pressure, applied power and gas composition are investigated to try to optimize the etch process. In general, the plasma density reaches a maximum near the wafer edge due to the so-called 'edge effect'. As a result, the etch rate is not uniform but will also reach its maximum near the wafer edge. The pressure seems not to have a big effect. A higher power increases the etch rate, but the uniformity becomes (slightly) worse. The gas mixing ratio has no significant effect on the etch process, except when a pure H 2 or N 2 plasma is used, illustrating the synergistic effects of a N 2 /H 2 plasma. In fact, our calculations reveal that the N 2 /H 2 plasma entails an ion-enhanced etch process. The simulation results are in reasonable agreement with the experimental values. The microscopic etch profile shows the desired anisotropic shape under all conditions under study.

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Section: Introductionmentioning

confidence: 99%

Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation

Laer

Tinck

Šamara

et al. 2013

Plasma Sources Sci. Technol.

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“…Hence, the degradation of reliability performance such as time dependent dielectric breakdown (TDDB) lifetime between Cu lines with vias is one of the most critical issues. Therefore, the self-aligned via process has been reported, [16][17][18][19] and the metal hard mask (MHM) process has been studied [20][21][22][23][24][25][26][27][28][29][30][31][32] instead of the conventional resist mask process to suppress the damage of interlayer dielectrics by the ashing process with oxygen (O 2 ) plasma. [33][34][35] We have studied the MHM process using the low stress TiN mask which had a fiber-textured structure for the perfect Cu filling and it has been demonstrated to be high performance.…”

mentioning

confidence: 99%

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

Torazawa

Matsumoto

Harada

et al. 2016

ECS J. Solid State Sci. Technol.

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High performance copper interconnects using extremely low-k film for the interlayer dielectric with the metal hard mask process and the interfacial surface oxygen treatment between extremely low-k film and liner layer was demonstrated. To suppress the process damage of interlayer dielectric and enlarge the space between vias and lines with a wide margin of lithography process, the robust extremely low-k film with the metal hard mask self-aligned via process was developed. The ultimate low capacitance wiring was achieved with the metal hard mask process, and the high reliability performance of time dependent dielectric breakdown between Cu lines with vias was accomplished by controlling the etching selectivity of the metal hard mask and the interlayer dielectrics. The adhesion strength between extremely low-k film and silicon carbide based liner layer was enhanced by controlling the composition of oxygen and carbon at the interface, resulting in the strengthening of the tolerance against chip packaging and thus the highly reliable chip packaging. This metal hard mask self-aligned via process with extremely low-k film and the interfacial surface oxygen treatment was demonstrated to be high performance, and therefore it offers a promising technology for Cu interconnects. Becoming the wiring pitches smaller as well as reducing the kvalue of dielectric materials are continuously required to achieve the high performance copper (Cu) interconnects which have higher speed, lower power and higher density. Thus, several kinds of lower k-value dielectric materials (k < 2.5) have been studied.1-12 However, they have posed many critical issues in the integration such as the degradation of film properties due to the post-process damages [13][14][15] and the weak tolerance against chip packaging due to the fragility of dielectric films and the weak adhesion strength between lower k-value dielectric materials and the underlying liner layer. In addition, shrinking both the size of via and the misalignment margin has essentially become difficult due to the technical limit of the lithography process. Hence, the degradation of reliability performance such as time dependent dielectric breakdown (TDDB) lifetime between Cu lines with vias is one of the most critical issues. Therefore, the self-aligned via process has been reported, [16][17][18][19] and the metal hard mask (MHM) process has been studied 20-32 instead of the conventional resist mask process to suppress the damage of interlayer dielectrics by the ashing process with oxygen (O 2 ) plasma. [33][34][35] We have studied the MHM process using the low stress TiN mask which had a fiber-textured structure for the perfect Cu filling and it has been demonstrated to be high performance. 36 However, the reports on the integration of lower k-value dielectric materials (k < 2.5) with the MHM self-aligned via process have been limited, and the complete process including reliability performance in chip packaging has not been reported.In this paper, high performance Cu interconnects using...

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Investigation of plasma etch damage to porous oxycarbosilane ultra low-kdielectric

Bruce¹,

Engelmann²,

Purushothaman³

et al. 2013

J. Phys. D: Appl. Phys.

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Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions

Cited by 4 publications

References 40 publications

Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation

Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

Investigation of plasma etch damage to porous oxycarbosilane ultra low-kdielectric

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Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions

Cited by 4 publications

References 40 publications

Etching of low-kmaterials for microelectronics applications by means of a N2/H2plasma: modeling and experimental investigation

Etching of low-kmaterials for microelectronics applications by means of a N2/H2plasma: modeling and experimental investigation

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

Investigation of plasma etch damage to porous oxycarbosilane ultra low-kdielectric

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Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation

Etching of low-kmaterials for microelectronics applications by means of a N₂/H₂plasma: modeling and experimental investigation