Study of Methods for Reducing Power Consumption and Area for a Digital Part of the Rfid-Tag

Abstract

The results of the development of a digital part for the low-frequency RFID tag and the results of power saving methods study in 180 nm, 90 nm and 45 nm CMOS processes are presented. Using of the presented methods allows to reduce the power consumption and area of the digital part by 400 % and by 50 %, respectively. For the target 180 nm CMOS process the maximum dynamic power is less than 1 μW, and the occupied area is 0.042 mm2.