Study of mask and wafer co-design that utilizes a new extreme SIMD approach to computing in memory manufacturing: full-chip curvilinear ILT in a day

Pang, Liang; Russell, E. Vidal; Baggenstoss, Bill; Lee, Michael; Digaum, Jennefir L.; Yang, Manman; Ungar, P. Jeffrey; Bouaricha, Ali; Wang, Kechang; Su, Bo; Pearman, Ryan; Fujimura, Aki

doi:10.1117/12.2534629

Cited by 17 publications

(43 citation statements)

References 12 publications

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“…In 2019, an entirely new approach, systematically designed for multibeam mask writers and GPU acceleration, made full-chip ILT a practical reality in production for the first time. 21 This new approach produced wafer results that confirmed a 100% improvement of the wafer process window versus OPC. Subsequent work in 2020, using a mask-wafer co-optimization (MWCO) technique, expanded these benefits and practical runtimes to ILT masks written by VSB mask writers.…”

mentioning

confidence: 83%

“…Figures 1 and 2 show one implementation of such an optimization. 21 Figure 1 shows the mask pattern, its simulated wafer contour, cost function, and cost gradient at the beginning of the optimization. It is clear that the wafer contour does not hit the wafer target, the cost function is not zero, and the cost gradient is not flat.…”

Section: Zzmentioning

confidence: 99%

“…Fig. 1 Mask pattern, simulated wafer contour and its target, cost function, and cost gradient at the beginning of the ILT optimization 21 (source: D2S). Fig.…”

Section: Zzmentioning

confidence: 99%

“…Full-chip, curvilinear ILT had finally become a practical reality. 21 The 2019 paper utilized newly introduced multibeam mask-writing technology. In 2020, D2S presented an MWCO technique that enabled the ILT computation approach from the 2019 paper to be applied to a memory mask written by a VSB writer.…”

Section: History Of Inverse Lithographymentioning

confidence: 99%

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Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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mentioning

confidence: 83%

Section: Zzmentioning

confidence: 99%

“…Fig. 1 Mask pattern, simulated wafer contour and its target, cost function, and cost gradient at the beginning of the ILT optimization 21 (source: D2S). Fig.…”

Section: Zzmentioning

confidence: 99%

Section: History Of Inverse Lithographymentioning

confidence: 99%

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Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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“…For full-chip OPC tasks, the biggest barrier to conventional methods is the runtime overhead. Pang et al [15] presented D2S to create full-chip ILT in a single day with giant GPU/CPU pairs, which consumes a large amount of resources on the handcrafted hardware and software. The learning-based methods, to the best of our knowledge, have not achieved any progress on full-chip mask optimization due to the dataset limitation and the low wafer pattern fidelity.…”

Section: Introductionmentioning

confidence: 99%