Study of Fatigue Behavior of 300 nm Damascene Interconnect Using High Amplitude AC Tests*

Abstract

The AC fatigue test technique, which uses cyclic joule heating to apply thermal cycles to thin-film structures, was applied to copper lines and vias in damascene dielectric structures on silicon substrates. Specimen chips with two different types of dielectric, oxide and low-k, were tested. The lines were 300 nm wide; various via widths were tested. At 100 Hz, cyclic temperature ranges from 400 to 900 ∫C produced line lifetimes between 10 and 1 million seconds. Similar lifetimes were reached in the vias for temperature ranges between 100 and 500 ∫C. When the data were plotted either as number of load reversals to failure or as lifetime against cyclic temperature range, the trends for the two different types of dielectric were indistinguishable. The temperature values at the one-reversal intercept for both types of dielectric were above 1000 ∫C. The via data were more scattered, but trended toward a lower intercept temperature.

Constraint effect in deformation of copper interconnect lines subjected to cyclic Joule heating

“…Practically all of the studies to date on cyclic Joule heating have reported on unconstrained conductive metal lines on substrates, but some studies of buried lines have been reported [12,15,18,19]. The behaviour of conductors buried within a dielectric structure is expected to be influenced by the constraint exerted by the surrounding structure.…”