Study of Current Flow Mechanisms in a CdS/por-Si/p-Si Heterostructure

Tregulov, V. V.; Litvinov, V. G.; Ermachikhin, A. V.

doi:10.1134/s1063782618070242

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…Porous silicon consists of a network of nanoscale sized silicon wires and voids which formed when crystalline silicon wafers are etched electrochemically in hydrofluoric acid based electrolyte solution under constant anodization conditions. The precise control of porosity and thickness allows the tailoring of optical properties of porous silicon and has opened the door to a multitude of applications in optoelectronics technology [10][11][12]. Such structures consist of silicon particles in several nanometer size separated by voids.…”

Section: Introductionmentioning

confidence: 99%

Nanostructured Cu2ZnSnS4 Thin Films on Porous-Si Wafer

Jafarov¹,

Nasirov²,

Jahangirova³

et al. 2019

J. Mater. Appl.

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Nanostructure CZTS thin film was fabricated by electrodeposition technique. To manufacture the heterojunctions, p-type c-Si wafers of (100) orientation were used as a substrate. Before anodization, the surface of the c-Si substrates were etched in an aqueous solution of HF and further washed in distilled water (at temperature of 80°С and ethyl alcohol and then dried in air. The current-voltage characteristics of the CZTS /PS solar cell under dark conditions show that forward bias current variation approximately exponentially with voltage bias. The capacitance for Nano- CZTS /PS Solar Cell decreases with the increase of the reverse bias voltage and with the increasing of etching time of nPS layers. That heterojunctions demonstrate good photo-response in the wavelength range of 510 - 650 nm.

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Section: Introductionmentioning

confidence: 99%

Nanostructured Cu2ZnSnS4 Thin Films on Porous-Si Wafer

Jafarov¹,

Nasirov²,

Jahangirova³

et al. 2019

J. Mater. Appl.

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“…Figure 1, a presents the static CVC of the studied EuGa 2 S 4 :Er 3+ crystal measured at room temperature. The following regions may be identified in this CVC: an Ohmic region, which extends up to a voltage of ∼ 800 V; a nonlinear region in the 800−1150 V interval; and a region of steep current rise that ends with breakdown at ∼ 1300 V. The passage of current in semiconductors in the nonlinear CVC region may be attributed to carrier injection from metal electrodes into a semiconductor in relatively weak electric fields and to field ionization of impurity trapping centers (or injection and field ionization acting simultaneously) in strong fields [8].…”

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confidence: 99%

Investigation of the phenomenon of current transition EuGa-=SUB=-2-=/SUB=-S-=SUB=-4-=/SUB=-:Er-=SUP=-3+-=/SUP=- crystals

Tagiyev O. B.,

Kazimova F. A.,

Hadjiyeva G. S.

et al. 2023

Technical Physics Letters

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The results of studying the static current-voltage characteristics of EuGa2S4:Er3+crystals at room temperature are presented. The mechanism of current passage in them is revealed. The height of the potential barrier at the metal-semiconductor interface (0.9 eV), the relative permittivity of crystals (3.1), and the concentration of traps (N~ 7.14· 1016 cm-3) were calculated, and the shape of the potential well for the electrons trapped in the traps was determined Keywords: current-voltage, metal-semiconductor, crystals, potential barrier,erbium

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Study of Current Flow Mechanisms in a CdS/por-Si/p-Si Heterostructure

Cited by 2 publications

References 5 publications

Nanostructured Cu2ZnSnS4 Thin Films on Porous-Si Wafer

Nanostructured Cu2ZnSnS4 Thin Films on Porous-Si Wafer

Investigation of the phenomenon of current transition EuGa-=SUB=-2-=/SUB=-S-=SUB=-4-=/SUB=-:Er-=SUP=-3+-=/SUP=- crystals

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