Study, Design and Analysis of 8 bit MIPS Processor using deepsubmicron CMOS C5 process

Shukla, Divya; Johari, Ayoush

doi:10.1109/icacat.2018.8933743

Cited by 1 publication

(1 citation statement)

References 7 publications

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“…These CGRAs would boost mobile device performances [1]. They are intended to increase the output of mobile apps [2]. Thus, the development of the CGRA software environment is difficult because of the different features and implementations of the CGRA hardware architecture.…”

Section: Introductionmentioning

confidence: 99%

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Phani.T¹

2021

TURCOMAT

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Coarse-Grained Reconfigurable Architectures (CGRA) is an effective solution for speeding up computer-intensive activities due to its high energy efficiency and flexibility sacrifices. The timely implementation of CGRA loops was one of the hardest problems in the analysis. Modulo scheduling (MS) was productive in order to implement loops on CGRAs. The problem remains with current MS algorithms, namely to map large and irregular circuits to CGRAs over a fair period of compilation with restricted computational and high-performance routing tools. This is mainly due to an absence of awareness of major mapping limits and a time consuming approach to solving temporary and space-related mapping using CGRA buffer tools. It aims to boost the performance and robust compilation of the CGRA modulo planning algorithm. The problem with the CGRA MS is divided into time and space and the mechanisms between the two problems have to be reorganized. We have a detailed, systematic mapping fluid that addresses the algorithms of the time mapping problem with a powerful buffer algorithm and efficient connection and calculation limitations. We create a fast-stable algorithm for spatial mapping with a retransmission and rearrangement mechanism. With higher performance and quicker build-up time, our MS algorithm can map loops to CBGRA. The results show that, given the same compilation budget, our mapping algorithm results in a better rate for compilation. The performance of this method will be increased from 5% to 14%, better than the standard CGRA mapping algorithms available.

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Section: Introductionmentioning

confidence: 99%

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Phani.T¹

2021

TURCOMAT

View full text Add to dashboard Cite

show abstract

Study, Design and Analysis of 8 bit MIPS Processor using deepsubmicron CMOS C5 process

Cited by 1 publication

References 7 publications

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

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