STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

Abstract

This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

A low‐power charge‐based integrate‐and‐fire circuit for binarized‐spiking neural network

“…As introduced in Equation ( 1), the MAC component is the dominant computational operation in BSNN inference. The 2T-2R STT XNOR-based array in Pham et al 5 is adopted in this work to realize the fundamental MAC operation. Figure 1A shows a single row of the memory array.…”

“…However, STT-MRAM BNN suffers seriously from process variation and thermal fluctuations, which degrades the network accuracy. 5 Recently, several implementations of binary spiking neural network (BSNN) based on spintronics memory have been proposed, aiming to overcome drawbacks related to poor computation accuracy due to process variation. [6][7][8][9][10][11][12][13] Spiking neural networks (SNNs) naturally exhibit better fault tolerance capabilities.…”

“…To mitigate the energy cost from the current summing, the 2T‐2R STT‐MRAM XNOR cells were studied, and the MAC product is represented in the voltage domain instead. However, STT‐MRAM BNN suffers seriously from process variation and thermal fluctuations, which degrades the network accuracy 5 …”

SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing

“…Although the SIMPLY logic was originally proposed and validated for Resistive Random Access Memory (RRAM) devices [10], [11], [12], [13], recent investigations have extended its applicability to Spin-transfer Torque Magnetic Random-Access Memory (STT-MRAM) devices [14], [15]. The latter represents an appealing option for LIM applications owing to faster read/write operations, low standby power consumption, and high endurance [16], [17], [18], [19], [20], [21], [22], [23]. Spinorbit torque (SOT) MRAM technology has also been considered as a potential alternative for the development of Compute-in-Memory (CIM) architectures [24], [25], [26].…”

Energy efficient ternary computation unit using differential spin Hall effect MRAM

“…Among the NVMs, spintronic-based MRAM devices are explored widely for in-memory logic computations. Spintransfer torque (STT)-MRAM has received a lot of attention in the in-memory computation for logic implementations because it is simple to integrate with CMOS technology and delivers efficient circuit design performance [3]. STT-MRAMbased nonvolatile logic in-memory architecture has been designed for QNNs.…”