STS-XYTER, a high count-rate self-triggering silicon strip detector readout IC for high resolution time and energy measurements

Kasiński, Krzysztof; Kłeczek, Rafał; Otfinowski, Piotr; Szczygieł, R.; Gryboś, P.

doi:10.1109/nssmic.2014.7431048

Cited by 25 publications

(15 citation statements)

References 6 publications

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“…This, however adds a challenge to the operation of RPCs, as these will have to be operated at low gain in order to match the available dynamic range of the ASIC. Some of the main features [26,27] Each ASIC consists of 128 analog channels which can convert analog signals into their corresponding digital forms. Each channel of the ASIC consists of a charge sensitive amplifier (CSA), a polarity selection circuit and two parallel signal processing paths defined by two pulse shaping amplifiers.…”

Section: Readout Chain At Gif++mentioning

confidence: 99%

Performance of a prototype bakelite RPC at GIF++ using self-triggered electronics for the CBM Experiment at FAIR

Mondal,

Dey,

Chattopadhyay

et al. 2022

Preprint

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The Muon Chamber (MuCh) is a sub-system of the Compressed Baryonic Matter (CBM) experiment for the detection of low-mass-vector mesons produced in high energy heavy ion collisions at beam energies ranging from 2 AGeV to 11 AGeV and decaying in the di-muon channel. MuCh consists of a segmented absorber and four detector triplet stations sandwiched between the absorber segments. At the 3 rd and 4 th stations of MuCh, Resistive Plate Chambers (RPCs) have been conceived for muon tracking. We have tested the performance of a low resistivity bakelite RPC prototype equipped with self-triggered front end electronics (MuCh-XYTER) for the CBM Muon Chamber. A systematic study on the muon detection efficiency and time resolution has been carried out in a high-rate photon background at the Gamma Irradiation Facility (GIF++) at CERN. The details of the measurement setup and the results are presented here.

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Section: Readout Chain At Gif++mentioning

confidence: 99%

Performance of a prototype bakelite RPC at GIF++ using self-triggered electronics for the CBM Experiment at FAIR

Mondal,

Dey,

Chattopadhyay

et al. 2022

Preprint

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“…The digital response to the accumulated charge in the readout pads is modelled following the properties of the readout ASIC, the STS/MUCH-XYTER (SMX) [15,16]. This ASIC features two shaping channels, the fast shaper used to determine the time stamp of the measurement, and the slow shaper which measures the charge amplitude by time-over-threshold.…”

Section: Digital Response Simulationmentioning

confidence: 99%

Development and implementation of a time-based signal generation scheme for the Muon Chamber simulation of the CBM experiment at FAIR

Singhal,

Chatterjee,

Friese

et al. 2021

Preprint

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A: The Compressed Baryonic Matter (CBM) experiment in the upcoming Facility for Antiproton and Ion Research (FAIR), designed to take data in nuclear collisions at very high interaction rates of up to 10 MHz, will employ a free-streaming data acquisition with self-triggered readout electronics, without any hardware trigger. A simulation framework with a realistic digitization of the detectors in the muon chamber (MuCh) subsystem in CBM has been developed to provide a realistic simulation of the time-stamped data stream. In this article, we describe the implementation of the free-streaming detector simulation and the basic data related effects on the detector with respect to the interaction rate.

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“…The production of components for the readout chain is ongoing. The key element for the readout of STS and MUCH detectors is the dedicated STS-MUCH-XYTER 2.2 (in short, SMX) ASIC developed by AGH in Kraków [1,2]. The SMX chip receives the pulses from the detector, digitizes and transmits them.…”

Section: Introductionmentioning

confidence: 99%

SMX and front-end board tester for CBM readout chain

Zabołotny,

Emschermann,

Gumiński

et al. 2021

Preprint

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A: The SMX chip is a front-end ASIC dedicated to the readout of STS and MUCH detectors in the CBM experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, FEB, or a full detector module. The software written in Python may easily be integrated with higher-level testing software.

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STS-XYTER, a high count-rate self-triggering silicon strip detector readout IC for high resolution time and energy measurements

Cited by 25 publications

References 6 publications

Performance of a prototype bakelite RPC at GIF++ using self-triggered electronics for the CBM Experiment at FAIR

Performance of a prototype bakelite RPC at GIF++ using self-triggered electronics for the CBM Experiment at FAIR

Development and implementation of a time-based signal generation scheme for the Muon Chamber simulation of the CBM experiment at FAIR

SMX and front-end board tester for CBM readout chain

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