Structure and process development of wafer level embedded SiP (System in Package) for mobile applications

Jung, Gi-Jo; Jeon, Byoung-Yool; Kang, Insoo

doi:10.1109/eptc.2009.5416553

Cited by 19 publications

(5 citation statements)

References 8 publications

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“…Also, the TBDB materials must remain stable in the process conditions through lithography, electroplating in the RDL and mold fabrication. [1][2][3][4][5][6][7] In this paper, laser releasable TBDB materials adaptable to a low temperature bonding process, and the release material with high durability through the FO-WLP process, is described.…”

Section: Introductionmentioning

confidence: 99%

UV Laser Releasable Temporary Bonding Materials for FO-WLP

Mizuno¹,

Ishii²,

Kato³

et al. 2018

Transactions of The Japan Institute of Electronics Packaging

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Temporary bonding/de-bonding (TBDB) technology in a FOWLP process is required to adapt to a low temperature process because of the potential for damage in handling the thin molded compound embedding dies. We have developed laser releasable TBDB materials for low temperature bonding processes that enable UV laser release with high throughput and low thermal/mechanical stress. The developed TBDB materials consist of two layers, an adhesive layer and a release layer. The appropriate wafer bonding temperature can be controlled by the molecular weight of the polymer which is the main component of the adhesive material. Good bonding property has been seen, even at 160°C by adopting the lowest molecular weight polymer. On the other hand, the release layer material exhibits excellent stability that allows for fabrication of RDLs directly onto the layer to give a stacked structure in the Chip-last (RDL-first) method. The laser energies preferred for wafer release processes are 130 mJ/cm 2 for a 308 nm excimer laser and 190 mJ/cm 2 for a 355 nm YAG. These materials will be promising for advancements of FO-WLP applications.

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Section: Introductionmentioning

confidence: 99%

UV Laser Releasable Temporary Bonding Materials for FO-WLP

Mizuno¹,

Ishii²,

Kato³

et al. 2018

Transactions of The Japan Institute of Electronics Packaging

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“…To satisfy various requirements, packaging technologies such as Flip-chip wafer bumping, PoP, 2.5D interposers, and 3D-TSV are under development. [1][2][3][4][5] These packaging structures require multilayered and/or fine-pitched Cu wiring. with high aspect ratio has been required for re-distribution layers.…”

Section: Introductionmentioning

confidence: 99%

Advanced Plating Photoresist Development for Semiconductor Packages

Sakakibara¹,

Akimaru²,

Hiro³

et al. 2016

Transactions of The Japan Institute of Electronics Packaging

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In recent years, novel electronic products like mobile phones, tablets, and personal computer have shrunk dramatically and become highly functionalized. To satisfy these market trends of smaller thinner devices, packaging technologies such as 3D-TSV, 2.5D, PoP and Flip-chip wafer bumping are being used. We have developed negative tone resists for redistribution layer, C4 and micro bumps. Our resist is negative tone resist which incorporates an acrylate cross-linker system with photo radical initiator. This formulation shows excellent chemical resistance to various plating solutions such as Cu, Ni, Sn/Ag and Au, with good stripability. The key technology of plating resists for advanced packages is high resolution, allowing for high aspect ratio patterning capability that covers a wide range of film thicknesses. An example of such applications is in advanced PoP package design which require a thick film material that has high resolution capability, along with high aspect ratio performance. Additionally, high resolution redistribution layer resists can be used to create fine pitch conditions which are necessary for package downsizing. Our resist shows good patterning performance from below 10 μm to above 100 μm film thickness conditions. In this paper, material design and key properties of novel plating resist with high resolution and high aspect ratio performance with a wide range film thickness ranges are discussed.

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“…With the demand increasing significantly in big data for the Internet of Things (IoT), advanced packaging technology of 2.5D or 3DIC TSV structures and fan-out wafer level packaging technology are being widely studied and developed [1][2][3][4][5]. The interconnection in advanced packaging has recently begun being stacked in the z direction, so packaging structures and their fabrication processes have become more and more complicated.…”

Section: Introductionmentioning

confidence: 99%

Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

Mukawa¹,

Takahashi²,

Kobata³

et al. 2016

J. Photopol. Sci. Technol.

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Novel bumping technology that can realize high density assembly of IC chips and packages with a high number of I/O is required in the field of electronic packaging. Recently, a novel bumping process called IMS (Injection Molded Solder) was proposed, which enabled direct injection of molten solder into the holes of a photoresist patterned array. In this paper, the current status of photoresist development and recent achievements for obtaining excellent solder filling rates are described. One of the important factors to obtain a high solder filling rate is reducing the amount of outgases from the photoresists at high temperature, as they prevent smooth solder filling into the photoresist holes. In order to solve such an issue, novel photoresists with high thermal stability have been designed and developed.

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Structure and process development of wafer level embedded SiP (System in Package) for mobile applications

Cited by 19 publications

References 8 publications

UV Laser Releasable Temporary Bonding Materials for FO-WLP

UV Laser Releasable Temporary Bonding Materials for FO-WLP

Advanced Plating Photoresist Development for Semiconductor Packages

Development of Liquid Photoresist for IMS (Injection Molded Solder) with High Thermal Stability

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