Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

Rzepka, Sven; Hofer, E.; Simon, E. R.; Meusel, E.; Reichl, H.

doi:10.1109/ectc.2001.927810

Cited by 14 publications

(5 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the temperature cyclic testing (TCT), temperature range of 218 K (−55 • C) to 398 K (125 • C) at the rate of 1 cycle/h was applied. 31 TCT is a test for fatigue life evaluation. It is cycled up to failure.…”

Section: Temperature Cyclic Testingmentioning

confidence: 99%

Thermomechanical Modeling of Electronic Packages

Jagannathan

Palaninathan

2011

Int. J. Model. Simul. Sci. Comput.

View full text Add to dashboard Cite

This paper is concerned with an integrated thermomechanical modeling and analysis of electronic packages. As the technology advances in terms of speed and density of circuit within a chip, the power dissipation increases exponentially. The packages are subjected to heating during fabrication, testing, and service. Due to the heterogeneous construction with wide mismatch of material properties, thermal stresses are induced which would result in mechanical failures such as cracking and delamination. It is essential to analyze the packages for thermal and stress fields and check their compliance with the design requirements. Earlier investigations were mostly based on approximate models such as plane-stress, plane-strain, and axisymmetric conditions. In reality, none of the packages satisfies the conditions associated with these models. In this work, 3D solid finite element with variable nodes, 8-21 nodes per element is employed. Software has been developed with the following features: sequentially coupled thermomechanical modeling, nonlinear transient solution capability, incompatible mode option when 8-node brick element is used, better estimation of nodal stresses by transformation from gauss point stresses, and quadratic criterion for delamination failure. A flipchip has been analyzed using the software developed for their thermal and stress fields. Numerical results indicate: the junction temperatures exceed the specification limits for higher heat dissipation, if appropriate cooling is not applied. The stresses in the die corner and at the solder balls are critical. Three-dimensional modeling is necessary for estimation of the same. Appropriate failure criterion was used in the failure prediction. Int. J. Model. Simul. Sci. Comput. 2011.02:45-66. Downloaded from www.worldscientific.com by UNIVERSITY OF QUEENSLAND on 08/15/15. For personal use only. Int. J. Model. Simul. Sci. Comput. 2011.02:45-66. Downloaded from www.worldscientific.com by UNIVERSITY OF QUEENSLAND on 08/15/15. For personal use only.

show abstract

Section: Temperature Cyclic Testingmentioning

confidence: 99%

Thermomechanical Modeling of Electronic Packages

Jagannathan

Palaninathan

2011

Int. J. Model. Simul. Sci. Comput.

View full text Add to dashboard Cite

show abstract

“…An important technique to dramatically increase the fatigue life of the flip-chip solder joints is to underfill the chip with an epoxy resin as shown in Figure 2.25. This helps to constrain the expansion mismatch between the chip and substrate [123] be used for package with and without underfill. In Eq.…”

Section: Thermo-mechanical Stresses and Its Failure Mechanismsmentioning

confidence: 99%

“…This impairs the performance of the underfill due to extra degrees of rotational in the cross-linked polymer which losses its benefits of coupling the die and the substrate. Underfill in its rubber state may even damage the solder joints [123].…”

Section: Thermo-mechanical Stresses and Its Failure Mechanismsmentioning

confidence: 99%

“…On underfill gap, simulation model concludes that the increase in solder height will increase the interface stresses but decrease the inelastic strain in the solder [130]. However, the gap determines the quality of related assembly parameters such as underfill flow and voids while the higher joints are more flexible and cause less plastic deformation for a given amount of chip to board displacement [123]. The substrate material has an effect on the thermo-mechanical stresses and affects its joint reliability.…”

Section: Thermo-mechanical Stresses and Its Failure Mechanismsmentioning

confidence: 99%

See 1 more Smart Citation

Flip chip joint-in-via architecture on flexible substrates with Au-Sn interdiffusion bonding

Lee¹

View full text Add to dashboard Cite

Pad pitch on substrate has been identified as a difficult flip-chip, which makes it a challenge to keep up with the microelectronic packaging revolution. This study proposes a joint-in-via architecture to meet this challenge but this research is hindered by the flux residues of conventional soldering. This study conceptualises the joint-in-via architecture and develops a fluxless bonding technique with its mechanism and reliability uncovered.

show abstract

“…Regions which will receive large amounts of stress usually have a higher node density than those which experience little or no stress [119]. FEA methodology is being used generally to solve the local electrical, thermal, and mechanical analyzing based on certain algorithm in a plain finite element model in the interconnect structures [120][121][122][123][124].…”

Section: Finite Element Analysismentioning

confidence: 99%

Investigating the electromigration reliability of copper interconnects

Shao¹

View full text Add to dashboard Cite

I would like to give an expression of my heartfelt gratitude to my supervisor, Professor Subodh G. Mhaisalkar, whose guidance and support has always been a source of motivation to me throughout the entire work. During three years of working with him, I learned to explore new ideas and to trust my abilities and intuition. He rendered an encouraging and productive atmosphere for me by accommodating sufficient space for my individualistic decisions as well as made sure that my research work remains on the right track. I take this opportunity to express that my gratitude towards him will remain afresh forever.

show abstract

Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

Cited by 14 publications

References 6 publications

Thermomechanical Modeling of Electronic Packages

Thermomechanical Modeling of Electronic Packages

Flip chip joint-in-via architecture on flexible substrates with Au-Sn interdiffusion bonding

Investigating the electromigration reliability of copper interconnects

Contact Info

Product

Resources

About