Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

Rzepka, Sven; Hofer, E.; Simon, E.; Meusel, E.; Reichl, H.

doi:10.1109/tepm.2002.1021638

Cited by 13 publications

(9 citation statements)

References 4 publications

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“…All cracks in real joints always start in their vicinity. [2] In Figure 6. high stress area was found in the top right corner of BT Substrate and solder joint.…”

Section: Critical Damage Pathsmentioning

confidence: 99%

Study on the Board Level Reliability of Lead-free PBGA Packages

Xue-jing

Yang

et al. 2006

2006 7th International Conference on Electronic Packaging Technology

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In this paper, a finite element modeling of lead and lead-free soldered PBGA package was performed. The inelastic stress and strain of the solder joints in the PBGA package under thermal cycling has been analyzed. The Garofalo-Arrheninus model was applied to describe the steady-state creep for the solders at high temperatures. The high-low temperatures extreme point, plastic strain, creep strain were analyzed in thermal cycling simulations. Various solder joint fatigue life was calculated by modified Coffin-Masson fatigue life prediction model. Finally, The fatigue life of three different solders in PBGA is compared.

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“…All cracks in real joints always start in their vicinity. [2] In Figure 6. high stress area was found in the top right corner of BT Substrate and solder joint.…”

Section: Critical Damage Pathsmentioning

confidence: 99%

Study on the Board Level Reliability of Lead-free PBGA Packages

Xue-jing

Yang

et al. 2006

2006 7th International Conference on Electronic Packaging Technology

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“…A 2D model with 1/2 symmetry, using plane strain elements, was used to save computation time (Plate 4). Although the absolute value of the calculated stresses is underestimated when using a 2D model, this approach is useful to analyse trends (Rzepka et al, 2002).…”

Section: Finite Element Modelmentioning

confidence: 99%

Delamination and solder flow‐out in underfilled and Pb‐free flip chips on laminate

Kleef

Bielen

Gülpen

et al. 2005

Microelectronics International

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Purpose -In land grid array hybrid or system in package type products passive integration on silicon dies are flip chip mounted on a laminate substrate using Pb-free solder. To increase the solder bump fatigue life, underfill is applied. The application of underfill resulted in the occurrence of an unexpected and unwanted phenomenon: solder flowing out of the underfill during a second level reflow test. The occurrence of solder flow-out seemed associated with moisturizing as part of a moisture sensitivity level assessment. The solder flow-out is preceded by delamination, initiated by mismatch in coefficient of thermal expansion between copper through-holes and laminate. This paper aims to describe the phenomenon and possible solutions by combining experiments with finite element (FE) simulations. Design/methodology/approach -Ways to prevent this kind of overstress failures are investigated by design of experiments and observed trends are compared with thermo-mechanical FE simulations. A significant contribution is made by through-holes close to the bump and underfill fillet. Findings -The FE simulations confirmed increased thermo-mechanical induced stress levels by bad positioning of vias, underfill and solder. The integrity of the flip chip construction is substantially improved by optimising product design, underfill material and the associated assembly process. Originality/value -This paper is a useful source of information on the causes of delamination and solder flow-out.

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“…However, the CTE mismatch has been larger in the first level of the assembly between silicon chip and PWB that may be reduce flip-chip bump reliability during the manufacturing process or thermal cycling. In the past, the thermally induced stresses and fracture mechanisms of the FC-CSP for IC have been numerically or experimentally investigated by researchers (Hong and Su 1998;Rzepka et al 2002;Tsai et al 2004). The relevant literature has indicated that the largest thermal stresses occurred in the solder bump and cracks propagated at the interface between the IC and solder bump.…”

Section: Introductionmentioning

confidence: 99%

Parametric study of flip-chip packaging for an MEMS device with diaphragm

Chuang

Wang

et al. 2010

Microsyst Technol

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A backside-etched silicon chip with a polysilicon diaphragm flip-chip attached on a printed wiring board and globally bumped on a FR4 printed circuit board was investigated through a finite element analysis for determining three key parameters of flip-chip chip size packaging, namely, the size of solder bump, and the thickness of the printed wiring board with/without U8437-3 underfill. Four kinds of thermal-induced stresses and deformations in the diaphragm, solder bump, and printed wiring board were evaluated for the parametric study. As the simulation results show, the thermal-induced stresses in the diaphragm and solder bump can be reduced effectively if the printed wiring board is thinner. However, the printed wiring board is still required to be sufficiently thick to prevent warping. In addition, the underfill material also can reduce the induced stress occurring at the interface between the solder joint and the chip and improve reliability. In general, the parametric study can provide a basis for the flip chip package of a MEMS device with a diaphragm, such as a MEMS microphone, MEMS pressure sensor, etc.

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Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

Cited by 13 publications

References 4 publications

Study on the Board Level Reliability of Lead-free PBGA Packages

Study on the Board Level Reliability of Lead-free PBGA Packages

Delamination and solder flow‐out in underfilled and Pb‐free flip chips on laminate

Parametric study of flip-chip packaging for an MEMS device with diaphragm

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