Streaming, low-latency communication in on-line trading systems

Subramoni, Hari; Petrini, Fabrizio; Agarwal, Virat; Pasetto, Davide

doi:10.1109/ipdpsw.2010.5470717

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…Pottathuparambil et al described an FPGA-based ITCH feed handler to handle a peak data rate of 420 Mbps with a deterministic latency of 2.7µs [13]. Subramoni et al presented a prototype of an on-line OPRA data feed decoder [14], achieving a latency of less than 4µs. Lockwood et al presented an FPGA IP library with networking, I/O, memory interfaces and financial protocol parsers [3].…”

Section: Latency Resultsmentioning

confidence: 99%

Exploring the potential of reconfigurable platforms for order book update

Luk

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-The order book update (OBU) algorithm is widely used in financial exchanges for rebuilding order books. The number of messages produced has drastically increased over time. The software solutions become more and more difficult to scale with the growing message rate and meet the requirement of low latency. This paper explores the potential of reconfigurable platforms in revolutionizing the order book architecture, and proposes a novel order book update algorithm optimized for maximal throughput and minimal latency. Our approach has three main contributions. First, we derive a fixed tick data structure for the order book that is easier to be mapped to the hardware. Second, we design a customized cache storing the top five levels of the order book to further reduce the latency. Third, we propose a hardware-friendly order book update algorithm based on the data structures we proposed. In the experiment, our FPGA-based solution can process 1.2-1.5 million messages per second with the throughput of 10Gb/s and the latency of 132-288 nanoseconds, which is 90-157 times faster than a CPU-based solution, and 5.2-6.6 times faster than an existing FPGA-based solution.

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Section: Latency Resultsmentioning

confidence: 99%

Exploring the potential of reconfigurable platforms for order book update

Luk

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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“…In addition to the algorithm optimization strategy, an important method for reducing system latency is to alleviate the latency generated by the operating system protocol stack. We can achieve this goal by using customized Network Interface Cards (NIC) embedded with specified software that bypass the OS kernel and network stack and improve the latency from 15-20 µs (Morris, Thomas, and Luk 2009) on a half round trip across the stack within an unoptimized system to 4 µs (Subramoni et al 2010). This method is also known as a standard software solution, and it dramatically lowers the latency by almost 90 percent.…”

Section: High-frequency Tradingmentioning

confidence: 99%

Automated trading systems statistical and machine learning methods and hardware implementation: a survey

Huang

Huan

et al. 2018

Enterprise Information Systems

108

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Automated trading, which is also known as algorithmic trading, is a method of using a predesigned computer program to submit a large number of trading orders to an exchange. It is substantially a real-time decision-making system which is under the scope of Enterprise Information System (EIS). With the rapid development of telecommunication and computer technology, the mechanisms underlying automated trading systems have become increasingly diversified. Considerable effort has been exerted by both academia and trading firms towards mining potential factors that may generate significantly higher profits. In this paper, we review studies on trading systems built using various methods and empirically evaluate the methods by grouping them into three types: technical analyses, textual analyses and highfrequency trading. Then, we evaluate the advantages and disadvantages of each method and assess their future prospects.

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“…Pottathuparambil et al described an FPGA-based ITCH feed handler [8] to handle a peak data rate of 420 Mbps with a deterministic latency of 2.7µs. Subramoni et al presented a prototype of an online OPRA data feed decoder [9], achieving a latency of less than 4µs. Lockwood et al presented an FPGA IP library with networking, I/O, memory interfaces and financial protocol parsers [2].…”

Section: B Related Workmentioning

confidence: 99%

A Nanosecond–Level Hybrid Table Design for Financial Market Data Generators

He²,

Luk

et al. 2017

2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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This paper proposes a hybrid sorted table design for minimizing electronic trading latency, with three main contributions. First, a hierarchical sorted table with two levels, a fast cache table in reconfigurable hardware storing megabytes of data items and a master table in software storing gigabytes of data items. Second, a full set of operations, including insertion, deletion, selection and sorting, for the hybrid table with latency in a few cycles. Third, an ondemand synchronization scheme between the cache table and the master table. An implementation has been developed that targets an FPGA-based network card in the environment of the China Financial Futures Exchange (CFFEX) which sustains 1-10Gb/s bandwidth with latency of 400 to 700 nanoseconds, providing an 80-to 125-fold latency reduction compared to a fully optimized CPU-based solution, and a 2.2-fold reduction over an existing FPGA-based solution.

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Streaming, low-latency communication in on-line trading systems

Cited by 15 publications

References 6 publications

Exploring the potential of reconfigurable platforms for order book update

Exploring the potential of reconfigurable platforms for order book update

Automated trading systems statistical and machine learning methods and hardware implementation: a survey

A Nanosecond–Level Hybrid Table Design for Financial Market Data Generators

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