Strained-Si heterostructure field effect transistors

Abstract

The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n-and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

“…We can see that the drain current and the transconductance are improved about 2.7 and 3.1 times respectively by using the stained-Si channel. The hole mobility enhancement factor due to 1% strain in Si is about 1.5 [12]. Therefore, the drivability improvement is mainly attributed to the hole SBH reduction between source and channel.…”

“…On the other hand, the strained-Si channel MOSFET has also received a great deal of attention recently due to its improved mobility [12]. A key processing issue to fabricate the strained-Si MOSFET is the low thermal budget to prevent strain relaxation and dislocation propagation from the buffer layers during processing.…”

A two-dimensional subthreshold current model for strained-Si MOSFET

“…Strained-Si technology offers device designers the ability to enhance carrier mobility and modify the band gap, which is compatible with the existent Si device process. Recently, research about this strain engineering has been reported [1][2][3][4][5][6][7].Reports on the threshold voltage model of strained-Si metal-oxide-semiconductor field-effect transistor (MOSFET) can be found [3]. However, there has been no research done on this device regarding the subthreshold current, which is one of the main parts of power consumption in deep submicron integrated circuits.…”

“…Strained-Si technology offers device designers the ability to enhance carrier mobility and modify the band gap, which is compatible with the existent Si device process. Recently, research about this strain engineering has been reported [1][2][3][4][5][6][7].…”

Tailoring strain in microelectronic devices

“…A few percent strain can increase the electron mobility µ in silicon by a factor of three [57][58][59], while at the same time the subthreshold current may . .…”