Strain-engineering in nanowire field-effect transistors at 3 nm technology node

Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors

“…Hence today's needs are more energy efficient transistors than conventional Si, which can ramp up the clock speed. In this perspective, strained-Si x Ge 1-x, along with advanced source/drain stressor design, seems to be a futuristic solution for new devices to come [22,27,28].…”

Impact of Ge clustering on the thermal conductivity of SiGe nanowires: atomistic simulation study

“…Silicon and silicon–germanium (SiGe) based nanostructures continue to be the focus of tremendous investment due to their widespread integration in nano- and optoelectronics, 1,2 solar cells, 3,4 thermoelectrics, 5–7 etc. Among the SiGe nanomaterials, one-dimensional SiGe alloy nanowires (NWs) have aroused widespread interest because they can function as a building block for nanoscale electronics and photonic systems.…”

Deep Insight Into Channel Engineering of Sub-3 Nm-Node P-Type Nanosheet Transistors With a Quantum Transport Model

“…Based on the above concerns, the channel engineering of pNS-FETs including that of crystal orientation, stress, and cross-sectional dimensions, needs extensive and profound consideration in a quantum transport scope. Strain/stress engineering takes a key position among all the technological innovations since it is cost-effective and its benefit on the device performance is comparatively large [6,8,10]. While tensile uniaxial strain/stress improves the device performance in n-type transistors [11], compressive strain/stress provides more significant hole mobility enhancement in ptype devices, because of its squeezing effect on the band structure yielding a decrease in overall m eff and an increase in group velocity [12,13].…”