Strain effects on three-dimensional, two-dimensional, and one-dimensional silicon logic devices: Predicting the future of strained silicon

Abstract

Using a classification scheme based on carrier confinement type (electrostatic and spatial) and the degrees of freedom of the mobile carriers (3DOF, 2DOF, and 1DOF), strain effects on 3DOF to 1DOF silicon logic devices are compared from quantum confinement and device geometry perspectives. For these varied device geometries and types, the effects of strain-induced band splitting and band warping on the modification of the average conductivity effective mass and carrier scattering rates are evaluated. It is shown that the beneficial effects of strain-induced band splitting are the most effective for devices with little or no initial band splitting and become less so for devices with already large built-in band splitting. For these devices with large splitting energy, the potential for strain-induced carrier conductivity mass reduction through repopulation of lower energy bands and the suppression of optical intervalley phonon scattering are limited. On the other hand, for all devices without spatial confinement, a comparable amount of effective mass reduction occurs through favorable strain-induced band warping. Under spatial carrier confinement, much higher strain levels with respect to unconfined or electrically confined devices are required to observe strain-induced band warping in the band structure, with larger strain requirements as the confinement dimension decreases. In electrically confined volume-inversion devices, the favorable strain type required for carrier mass reduction results in increased surface scattering by bringing the carrier centroid closer to gate surfaces. However, for spatially confined volume-inversion devices, the favorable mechanical strain does not alter the carrier distribution in the device cross section. Consequently, strain is expected to be more effective in modification of low field carrier transport in electrically confined volume-inversion devices and less for spatially confined devices, with respect to conventional 2DOF planar metal-oxide-semiconductor field-effect transistors. On the other hand, for high-field quasiballistic transport, spatially confined devices, have the highest potential for strain-induced modification of device ballisticity, since the carrier backscattering ratio strongly depends on the surface roughness scattering rate at the source-end of the channel.

Carrier mobility in strained Ge nanowires

“…[19][20][21] The mobility is also very sensitive to strains, 21 which provides real opportunities to engineer the transport properties of Si NW devices. 24 In this paper, we apply the same atomistic methods to the mobility in free-standing and strained Ge NWs. We present a detailed study of the mobility of electrons and holes versus size, orientation, and strain.…”

“…24 It is also known that the band structure of Ge NWs can be modulated by strains. 6,17 We have therefore investigated the transport properties of uniaxially strained Ge NWs.…”

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

“…Moreover the side-walls, with different crystallographic orientation, may also contribute to the total carrier mobility and modify the drain current [3]. Stress engineering can be used to further improve the device performance [2,4]. The combination of stress and NW architecture appears as a promising solution to scale further CMOS technology.…”

“…The reduced dimensions of the cross-section of nanowire below 20 nm can lead to the confinement of carriers and change the transport properties of NW devices [2]. Moreover the side-walls, with different crystallographic orientation, may also contribute to the total carrier mobility and modify the drain current [3].…”

Lattice strain distribution resolved by X-ray Bragg-surface diffraction in an Si matrix distorted by embedded FeSi2nanoparticles

“…It has been recognized, therefore, that not only structural defects but also lattice elastic stress/strain near to epilayer/substrate interfaces (for instance, originated by different thermal expansion coefficients) are factors that crucially influence device performance and reliability. In this context, it is of fundamental technological importance to detect and to quantify, with high resolution, in-plane and out-of-plane lattice strain distributions in low-dimensional structures, since an anisotropic strain may, for example, limit or enhance the injection or mobility of charge carriers in one of the x, y or z directions (Baykan et al, 2010). The term 'in-plane' refers to the xy plane, while 'out-ofplane' refers to the direction along the z axis.…”