Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors

Bobrek, Alex; Paul, JoAnn M.; Thomas, Donald E.

doi:10.1109/tc.2010.19

Cited by 10 publications

(12 citation statements)

References 15 publications

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“…Existing literature about frequency based experiments illustrates uniform single core processors where each processor carries their individual cycle speed covering real time workload characterization [4]. Based upon metric measurements the workload will be distributed to intended processor best suited to current application.…”

Section: Related Workmentioning

confidence: 99%

Efficiency Measurement for Effective Stress Management in Heterogeneous 2-D Mesh Processor

Singh¹,

Behal²,

Arora³

2013

IJCA

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Multi-Processor interconnection with varying speed is a great attempt in massive parallel processors. Such types of distributed cluster along with heterogeneous behavior will requires vast amount of scheduling efforts. Complexity increases as scheduler has to detect dynamic characteristics of the processors. Parallel schedulers are implemented in cluster technology for job assignment and placement. Further, core processor technology will provide a greater endeavor for load balancing. This research covers heterogeneous multiprocessors with 2-D mesh interconnection mapped to cube oriented memory mesh for job allocation and distribution. The job distribution will be based upon processor cycle speed. A two dimensional job slice is build, which in later stages along with many other slices overlapped to exhibit memory cube.

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Section: Related Workmentioning

confidence: 99%

Efficiency Measurement for Effective Stress Management in Heterogeneous 2-D Mesh Processor

Singh¹,

Behal²,

Arora³

2013

IJCA

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“…The Modeling Environment for Software and Hardware (MESH) permits performance and power evaluation when threads execute on sets of heterogeneous resources under a variety of custom schedulers [123], [124]. MESH explores CHM design above the level of the ISS, where designers deal with threads, processors, and memories instead of instructions, functional units, and registers.…”

Section: • Easy Debuggingmentioning

confidence: 99%

“…This approach is called execution-driven simulation with cross-profiling or back-annotation. It has been widely used for traditional multiprocessor simulation [127], as well as for simulation of CHM systems [128] [124]. These annotations capture the computational complexity of a program's code.…”

Section: • Easy Debuggingmentioning

confidence: 99%

“…Once a shared resource access is accessed, an annotation must be inserted to determine contention [124].…”

Section: • Easy Debuggingmentioning

confidence: 99%

“…Then, the designer must identify the locations in the code in which annotations need to be inserted. Annotations need to capture the control flow of a program [124]. Therefore, annotations are usually inserted at the end of every loop and in every path of the branch.…”

Section: • Easy Debuggingmentioning

confidence: 99%

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Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

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MVA-Based Probabilistic Model of Shared Memory with a Round Robin Arbiter for Predicting Performance with Heterogeneous Workload

Kawahara

Ono

Nakada

2013

Multicore Software Engineering, Performance, and Tools

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Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors

Cited by 10 publications

References 15 publications

Efficiency Measurement for Effective Stress Management in Heterogeneous 2-D Mesh Processor

Efficiency Measurement for Effective Stress Management in Heterogeneous 2-D Mesh Processor

Capacity metric for chip heterogeneous multiprocessors

MVA-Based Probabilistic Model of Shared Memory with a Round Robin Arbiter for Predicting Performance with Heterogeneous Workload

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