Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…Moreover, since power consumption is quickly becoming a first-class concern of circuit design, much effort is put into achieving power dissipation based on either analytical or empirical technologies, such as using some high-level power analysis tools [131,180,133], or modeling power analysis [23,171,84]. For these mathematical analysis models, large system complexity is a challenge, making the enumeration of the complete design logic difficult, sometimes an unfeasible task.…”

“…Actually, it is an unfeasible task to accurately predict latency of a complicated system by static models. Likewise, the power consumption analysis, such as using some high level power analysis tools [131,180,133] or modeling power analysis [23,171,64,84,49,90], suffers from more inaccuracies without gate-level parameters and switching activities. The high abstraction models are very hard to determine with accuracy in the early development stages.…”

“…An earlier stage performance evaluations, such as transfer latency [181] and wire efficiency models [108,88], and several high-level power analysis tools [133,64,90,171,84], allow engineers to design circuits more efficiently, reducing the time costs and risk of error involved in building circuit prototypes. For these mathematical analysis models, large system complexity is a challenge, making the enumeration of the complete design logic difficult, sometimes an unfeasible task.…”