STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS

CNN Inference Using a Preprocessing Precision Controller and Approximate Multipliers With Various Precisions

“…The core component in the PE is the multiplier. This design can be seen in the fixed-point CNN accelerators such as [16][17][18][19][20][21][22]. In addition to the floating-point accelerators such as [39][40].…”

“…Using fixed-point arithmetic to improve the performance of convolutional neural network (CNN) accelerators was proposed by the industry as can be seen in the articles published by Qualcomm in [14] and IBM in [15]. Additionally, several application-specific integrated circuit (ASIC) designs for fixed-point CNN accelerators have been proposed in the literature such as [16][17][18][19]. Using a 16-bit base for the design of ASIC CNN accelerators is common as can be seen in [16][17][18].…”

“…Based on the architectures in [16][17][18][19][20][21][22], CNN accelerators are designed using arrays of processing elements (PEs), at the core of each PE, a multiply and accumulate (MAC) unit exists. Hence, the multiplier is a primary component in the design of CNN accelerators, and any improvement in the performance of the multiplier will scale up to improve the performance of the entire accelerator.…”

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching

“…2) Parallel Additions One of the key issues in sparse DNN processing architecture is high area/power overhead of accumulation due to irregular output data [34], [35]. In this article, we reduce the psum overhead by reducing psum register access by reserving a spatial redundant addition network.…”

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing

“…Since AlexNet achieved outstanding achievements in the ImageNet Large-Scale Visual Recognition Challenge (ILSVRC), a lot of research teams have been devoted to the development of convolutional neural networks (CNNs) with well-known research advances such as ZFNet, GoogleNet, VGG, ResNet, etc. Owing to the increasing demand for real-time applications, an efficient dedicated hardware computation unit (i.e., a CNN accelerator) is required to support the calculations [ 1 , 2 , 3 , 4 , 5 , 6 ] in the inference process. Moreover, for edge devices, low power is also an important concern [ 7 , 8 , 9 ].…”