1998
DOI: 10.1016/s0026-2714(97)00166-2
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STI process steps for sub-quarter micron CMOS

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Cited by 19 publications
(5 citation statements)
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“…STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, deposition of one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization [6]. Defects can be either inherently present in the bulk silicon or generated during some critical process steps like epitaxial growth, implantation, and the formation of shallow trench isolations [7][8].…”
Section: ) Traditional Screening Procedures For Stimentioning
confidence: 99%
“…STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, deposition of one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization [6]. Defects can be either inherently present in the bulk silicon or generated during some critical process steps like epitaxial growth, implantation, and the formation of shallow trench isolations [7][8].…”
Section: ) Traditional Screening Procedures For Stimentioning
confidence: 99%
“…The increasing implementation of Chemical Mechanical Polishing (CMP) 2 in semiconductor manufacturing coupled with the limitations of the LOCOS technique has led to the acceptance of Shallow Trench Isolation (STI) as the technique of choice for device isolation 3,4 . The increasing implementation of Chemical Mechanical Polishing (CMP) 2 in semiconductor manufacturing coupled with the limitations of the LOCOS technique has led to the acceptance of Shallow Trench Isolation (STI) as the technique of choice for device isolation 3,4 .…”
Section: Neededmentioning
confidence: 99%
“…11 A silicon wafer, shallow trench isolation (STI), an inter-layer dielectric (ILD) and the establishment of interconnects are all CMP processing areas. [12][13][14][15] CMP has recently expanded its applications to include microelectromechanical devices, printed circuit boards and more. [16][17][18][19][20] The CMP process removes material through chemical action including slurry chemicals and abrasives, along with mechanical abrasion.…”
Section: Introductionmentioning
confidence: 99%