Steady-State Dead-Time Compensation in VSI

Abronzini, Umberto; Attaianese, C.; D’Arpino, Matilde; Monaco, Mauro Di; Tomasso, G.

doi:10.1109/tie.2016.2586680

Cited by 52 publications

(23 citation statements)

References 28 publications

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“…At the same time, the output power quality of the converter should not be ignored either. Among the factors affecting the power quality, the dead-time effect can generate quantities of low-frequency harmonics in the output current [16], [17], which should be also well addressed.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, numerous dead-time compensation schemes have also been investigated. In [17], a steady-state dead-time compensation is proposed, where the error between the real current and the reference one is used to determine the voltage error and the suitable time shift for the switching pattern within each sampling interval. A vector-based dead-time compensation is proposed in [18], and a dead-time error voltage vector is introduced to adjust the reference voltage vector depending on the load current polarity.…”

Section: Introductionmentioning

confidence: 99%

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A Combined DPWM Based on DSOGI-FLL for Switching-Loss Reduction and Dead-Time Compensation

et al. 2020

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High efficiency and high output power quality of converters are always two goals pursued in power electronic systems. In this paper, the conventional discontinuous pulse width modulation (DPWM) for switching-loss reduction and a modified time-based dead-time compensation for reducing output current harmonics are investigated. And a combined DPWM for switching-loss reduction and dead-time compensation is proposed, where the amplitude adjustment and the zero-sequence injection in modulation waves are carried out separately in different current intervals related to polarities of three-phase currents. Moreover, in order to detect accurate polarities of the three-phase currents with ripples and harmonics, the secondorder generalized integrator frequency-locked loop (DSOGI-FLL) is adopted and inserted into the combined DPWM. Finally, a combined DPWM based on DSOGI-FLL is proposed for switching-loss reduction and dead-time compensation. The comparison of experimental results with several PWM schemes verifies that, the proposed PWM scheme can both effectively reduce the switching loss and compensate the dead-time, simultaneously enhancing the efficiency and the output power quality of the converter. INDEX TERMS Dead-time, discontinuous pulse width modulation (DPWM), second-order generalized integrator frequency-locked loop (DSOGI-FLL), switching loss.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Combined DPWM Based on DSOGI-FLL for Switching-Loss Reduction and Dead-Time Compensation

et al. 2020

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“…With the development of power electronics technology, voltage source inverters have been widely used [1][2][3][4]. The power semiconductor devices of the inverter and its control circuit constitute the weakest link, which is vulnerable to being faulty.…”

Section: Introductionmentioning

confidence: 99%

A Secondary Reconfigurable Inverter and Its Control Strategy

Xiang

Chen

2020

Applied Sciences

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This article proposes a topology of the secondary reconfigurable inverter and the corresponding fault-tolerant control strategy. When the secondary reconfigurable inverter is operating normally, its topology structure is the TPSS circuit. When the power semiconductor devices in the inverter are faulty, the inverter circuit needs to be reconfigured. After removing the faulty power semiconductor devices, the remaining power semiconductor devices and the DC side powers are reconstructed as the TPFS structure to keep the system running normally. This article also proposes a switch-pulse-resetting algorithm. This paper adopts the control strategy connecting the constant-voltage, constant-frequency control method with the switch pulse resetting algorithm. It need not change the control algorithm when the proposed reconfigurable inverter is transformed from the normal running state into the faulty running state. The inverter dependability is greatly improved. Finally, the feasibility and effectiveness of the proposed second reconfigurable inverter topology and control strategy are verified by simulation and experiment.

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“…The widespread adoption of Voltage Source Inverters (VSIs) has pushed research forward in the development of new power converter topologies and modulation techniques, which take into account the non-linear behavior of power semiconductors and components with the aim of improving the performance of the whole power conversion system [1][2][3]. In medium-and high-power applications, Neutral Point Clamped (NPC) inverters [4] are prevailing over conventional two-level VSIs, thanks to their high performance, such as reduced stress on semiconductors, less switching losses, lower Electromagnetic Interference (EMI), and improved harmonic content thanks to the n levels of the output voltage waveform.…”

Section: Introductionmentioning

confidence: 99%

Induction Motor Drives Fed by an NPC Inverter with Unbalanced DC-Link

et al. 2019

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Neutral Point Clamped (NPC) converters with n levels are traditionally controlled in such a way that the DC-link capacitors operate at 1/(n−1) of the total DC-link voltage level. The voltage level across the DC-link capacitors has to be properly regulated by the capacitor unbalance control to contain the harmonic distortion of the converter output voltages. State-of-the-art modulation techniques address the problem of the DC-link voltage regulation for NPC inverters. However, they highly show reduced performance when unbalanced DC-link voltages are considered. In this paper, a novel Space Vector Modulation (SVM) is proposed for NPC converters with an unbalanced DC-link. At every modulation interval, the technique defines the optimal switching pattern by considering the actual unbalanced DC-link conditions. The proposed modulation allows improving the harmonic content of the NPC converter output voltage with respect to a traditional ML-SVM, when the same operating conditions are considered. As an extension, the proposed modulation technique will guarantee the same output voltage quality of a traditional ML-SVM with unbalanced DC-link, while improving the conversion efficiency thanks to a reduction of switching frequency.

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Steady-State Dead-Time Compensation in VSI

Cited by 52 publications

References 28 publications

A Combined DPWM Based on DSOGI-FLL for Switching-Loss Reduction and Dead-Time Compensation

A Combined DPWM Based on DSOGI-FLL for Switching-Loss Reduction and Dead-Time Compensation

A Secondary Reconfigurable Inverter and Its Control Strategy

Induction Motor Drives Fed by an NPC Inverter with Unbalanced DC-Link

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