Steady State Analysis of a Three Node Tandem Communication Network Model with DBA having Homogeneous Compound Poisson Direct Bulk Arrivals at Node 1 And Node 2

Abstract

In this paper, a three stage communication network model with two stage homogeneous bulk arrivals and dynamic bandwidth allocation under equilibrium condition is developed and analyzed. Consider a Communication network in which three nodes are in tandem and the messages arrive to the first node are converted into number of packets and stored in first buffer connected to the first node. After transmitting from the first node, the messages arrive to the second node from first node and the messages which are directly arriving to the second node are converted into number of packets and stored in second buffer connected to the second node. After transmitting from the second node, the messages arrive to the third node are converted into number of packets and stored in third buffer connected to the third node. Dynamic Bandwidth Allocation (DBA) is the strategy that the transmission rate at each node is adjusted depending upon the content of the buffer at every packet transmission. It is assumed that the arrival of packets follow compound Poisson processes and the transmission completions at each node follow Poisson processes. The steady state analysis of this model is carried by assuming that the system is stable under equilibrium. This model is more accurately fit into the realistic situation of the communication network having a predecessor and successor nodes for the middle node. Using the difference-differential equations, the joint probability generating function of the number of packets in each buffer is derived. The performance measures like, the probability of emptiness of the three buffers, the mean content in each buffer, mean delays in buffers, throughput etc. are derived explicitly under equilibrium or steady state conditions. This network model is much useful in communication systems. KeywordsThree stage communication networks, Dynamic bandwidth allocation, Batch arrivals and Steady state.