STDP implementation using multi-state spin−orbit torque synapse

Ghanatian, Hamdam; Ronchini, Margherita; Farkhani, Hooman; Moradi, Farshad

doi:10.1088/1361-6641/ac419c

Cited by 6 publications

(3 citation statements)

References 51 publications

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“…In both, seven i-SOT-MTJs are utilized to create an ADC with 3 bits of resolution. By engineering the w HM , I SOT,crit s can be tuned so that by increasing w HM , the required current for switching the MTJ will increase 29 . To this end, w HM of each MTJ should be properly designed to ensure that I SOT,crit s for MTJ 1 , MTJ 2 , …, MTJ 7 are equal with I SOT,crit , 2 I SOT,crit , 3 I SOT,crit , …, and 7 I SOT,crit , respectively.…”

Section: Spin-cmos Adcmentioning

confidence: 99%

Spin–orbit torque flash analog-to-digital converter

Ghanatian¹,

Benetti²,

Anacleto³

et al. 2023

Sci Rep

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Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

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Section: Spin-cmos Adcmentioning

confidence: 99%

Spin–orbit torque flash analog-to-digital converter

Ghanatian¹,

Benetti²,

Anacleto³

et al. 2023

Sci Rep

Self Cite

View full text Add to dashboard Cite

show abstract

“…In both, seven SOT-based MTJs are utilized to create an ADC with 3 bits of resolution. By engineering the wHM, ISOT,crits can be tuned so that by increasing wHM, the required current for switching the SOT-based MTJ will increase 25 . To this end, wHM of each MTJ should be properly designed to ensure that ISOT,crits for SOT-based MTJ1, SOT-based MTJ2, …, SOT-based MTJ 7 are equal with ISOT,crit, 2ISOT,crit, 3ISOT,crit, …, and 7ISOT,crit, respectively.…”

Section: Spin-cmos Adcmentioning

confidence: 99%

A 3-Bit Flash Spin-Orbit Torque (SOT)-Analog-to-Digital Converter (ADC)

Ghanatian

Farkhani

Rezaeiyan

et al. 2022

IEEE Trans. Electron Devices

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In this paper, a 3-bit Flash spin-orbit torque analog to digital converter (SOT-ADC) is presented which works based on switching of a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) by spin Hall effect (SHE) assisted by spin-transfer torque (STT). To quantize the input signal into 8 states, a heavy metal (HM) with different cross-sectional areas that is shared with seven MTJs is utilized. To enable the deterministic switching, STT currents are employed. However, such currents make challenges during conversion and sensing phases which are addressed in this work. The SOT-ADC eliminates the (2 n -1)-time duplication of the input current (Iin) in conventional n-bit current mode CMOS Flash ADCs. Each MTJ acts as a comparator that compares the input signal (current) with its own critical current (IC) as a reference current (Iref). Therefore, the power-hungry comparators in CMOS Flash ADCs can be replaced by simple latch-based comparators for sensing the states of MTJs. Moreover, instead of using different sizes of transistors to create various values of Iref i.e., Iref1, 2Iref1 … fixed currents as sensing currents are used which leads to reducing mismatch issue and chip area. Because of the influence of the resistance of HM, each MTJ has an exclusive reference voltage (Vref) that is created by a dummy 3-bit SOT-quantizer. According to simulation results, power consumption and maximum sampling rate (including all conversion, sensing, and reset phases) of the ADC are 416 µW and 102 MS/s in 180 nm CMOS technology, respectively. In addition, the differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.258 least significant bit (LSB) and -0.275 LSB, respectively.Index Terms-Flash analog to digital converter (ADC), spin-orbit torque (SOT), spin-transfer torque (STT), magnetic tunnel junction (MTJ).

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“…restricted by the von Neumann architecture with unique implicit analogue capabilities such as ultra-low power consumption, robustness and efficient parallel computing [1][2][3][4][5][6][7][8]. Furthermore, it emphasizes on highly effective neuromorphic systems with fault tolerance and self-learning characteristics by overcoming the traditional von Neumann bottleneck.…”

Section: Introductionmentioning

confidence: 99%

A recurrence model capturing interface traps for non-zero bandgap GFETs towards dynamic mimicking of synaptic plasticity

Chandrasekar,

Raja Shaik,

Rajakumari

et al. 2024

Semicond. Sci. Technol.

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This paper is primarily focused on developing an analytical model to mimic the synaptic behavior with non-zero bandgap of boron (B)/nitrogen (N) substitution doped graphene field effect transistors (GFET). The trap charges at the channel and gate-insulator interface are utilized to induce the hysteresis conduction mechanism, which further is exploited to accomplish the synaptic plasticity. The proposed recurrence i.e., time dependent trap states drain current model is well capturing the physical insights of trap charges through an equivalent MIG (metal-insulator-graphene) model. The interesting fact of the proposed model is that it is compatible with both the doped (B/N) as well as with the undoped GFET. The model is also explored to generate the hysteresis characteristics of the GFET that is further utilized for mimicking the synaptic behavior. Another fact needs to be noticed is the existence of complete off regions for doped B/N GFET unlike the undoped case that manifests the undesirable ambipolar behaviour. As a result, the synapse made up of B/N doped GFET is predicting an optimistic learning and memory mechanism, termed as spike time dependent plasticity (STDP). The STDP characteristics of B/N doped synaptic GFET has been enhanced by more than 18$\times$ when compared against the artificial synapse made by undoped GFET. Hence, the hysteresis behaviour along with non-zero bandgap of B/N substitution doped GFETs make it highly favourable in dynamic mimicking of synaptic plasticity with efficient biologically plausible.

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STDP implementation using multi-state spin−orbit torque synapse

Cited by 6 publications

References 51 publications

Spin–orbit torque flash analog-to-digital converter

Spin–orbit torque flash analog-to-digital converter

A 3-Bit Flash Spin-Orbit Torque (SOT)-Analog-to-Digital Converter (ADC)

A recurrence model capturing interface traps for non-zero bandgap GFETs towards dynamic mimicking of synaptic plasticity

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