Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing

Farrokhbakht, Hossein; Gratz, Paul V.; Krishna, Tushar; Miguel, Joshua San; Jerger, Natalie Enright

doi:10.1109/hpca53966.2022.00074

Cited by 7 publications

(3 citation statements)

References 34 publications

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“…Compared with VC, SDM has higher network throughput performance. SDM uses virtual circuits to transmit messages [20]. An exclusive part of a virtual circuit channel bandwidth is responsible for transmitting the entire message.…”

Section: Flow Control Methodsmentioning

confidence: 99%

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

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Section: Flow Control Methodsmentioning

confidence: 99%

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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“…There are studies in the literature studying adaptive NoCs [ 19 , 20 ] to improve application parallelism abilities and fast path NoCs [ 21 , 22 , 23 ], which improves latency and throughput by redesigning the PS routers. Adapt-NoC [ 20 ] introduces a reinforcement learning (RL)-based control policy.…”

Section: Related Workmentioning

confidence: 99%

“…Multi-hop bypassing has been researched intensively to design a near-optimal interconnection network [ 21 ]. FastPass [ 22 ] promotes a packet to traverse the network bufferlessly, and provides multiple pre-defined non-overlapping lanes. FastPass can transfer packets via the pre-defined non-overlapping lanes to guarantee that the packet is not blocked by congestion or deadlock.…”

Section: Related Workmentioning

confidence: 99%

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

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Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

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Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC

Soliman,

Feng,

Shengqiang

et al. 2024

Microprocessors and Microsystems

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Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing

Cited by 7 publications

References 34 publications

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC

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