Statistics for parallelism and abstraction level in digital simulation

Abstract

This paper presents statistics of several designs at four design abstraction levels -the instruction, behavioral, RTL, and gate levels. The data includes simulation time profiles, maximum speedup and limitations of parallelism, typical model evaluation times, event distributions, element intensities, and component counts for the four abstraction levels. This data is then used to analyze and evaluate several speed-up approaches: mixed-level simulation, parallel software simulators, parallel pipelined hardware accelerators, and decreased time resolution. modern systems, or particular accelerators which do not generalize to other techniques. Furthermore, the published data present statistics only at the gate/switch level; no comparisons have been done between abstraction levels.Some of the more comprehensive data at ttie gate level are presented in3, 4.The results show that element activity is around 0.1 to 0.5% at any particular time point. For the example circuits (3400 gates, 5000 gates, and 150,000 transistors), simulations show that parallelism can obtain speed-ups between 10-30. We found a factor of roughly ten speed-up between each of the abstraction levels.This paper presents detailed simulation statistics of three designs: A pipelined 8080 micro-processor, a 16x16 bit multiplier, and a 32 bit RISC processor (MIPS-X). We wrote descriptions of the 8080 and the multipljer at the four abstraction levelsinstruction, behavioral, RTL, gate -so performance and time profiles could be analyzed. We describe how the simulations differ from design to design, level to level, how parallelism is affected by the representation level, and the limits of parallelism. We also analyze the inherent overhead of an event-driven environment and when it makes sense to use a non event-driven simulator.

Analysis and Simulation of Mixed-Technology VLSI Systems

“…Soulé and Blank [43] investigated the available parallelism in a model of the 8080 microprocessor, consisting of 3439 gates, or LPs. Their study showed that, at any given time segment during the simulation, only 0.1-0.5% of the LPs were active and that only 10-20% of the LPs were active during each microprocessor clock cycle.…”