Statistical variations in VCO phase noise due to upconverted MOSFET 1/f noise

Erturk, M.; Xia, Tian; Wolf, Randy; Scagnelli, D.P.; Clark, William F.

doi:10.1109/rfic.2008.4561430

Cited by 7 publications

(2 citation statements)

References 6 publications

(11 reference statements)

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“…However, few studies focus on lowfrequency (LF) noise degradation under actual RF operating conditions. The LF noise of MOSFETs is a very important parameter in RF circuit applications because it gives rise to phase noise in oscillators or multiplexers [7,8]. The LF noise performance of MOSFET under various kinds of hot-carrier DC stress has been successfully studied [9,10,11,12,13,14,15,16], but MOSFET's in real circuits are exposed to the transient gate and drain voltage conditions.…”

Section: Introductionmentioning

confidence: 99%

Impact of RF stress on the low-frequency noise in nMOSFETs

Niu

Yang

et al. 2021

IEICE Electron. Express

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In this paper, the degradation of low-frequency (LF) noise under different RF stress conditions in nMOSFETs has been reported and compared with the conventional DC stress condition. LF noise increases after RF stress and the increment of noise under RF stress at a large V gs value is bigger than that caused by DC stress. The change in LF noise intensity under RF stress raised more rapidly at large V gs values than that at small V gs values, which are contradictory to LF noise performance after DC stress. The influence of the input power and frequency of stress on LF noise has also been investigated separately. As the stress input power or frequency increases, the increment of noise intensity rises as well. The γ decreases as the growth of the stress input power or frequency, and the values of γ are below 1 after 18 GHz RF stress. The results provide experimental verification that the interface traps generated by RF stress play a major role in the degradation of LF noise.

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Section: Introductionmentioning

confidence: 99%

Impact of RF stress on the low-frequency noise in nMOSFETs

Niu

Yang

et al. 2021

IEICE Electron. Express

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“…Process variations, including inter-die variations and local mismatches, significantly impact the parametric yield of analog/RF circuit, and must be properly handled at all levels of design hierarchy [1]- [2]. Traditional approaches based on overdesign [3]- [4] are not sufficient to maintain high parametric yield [5]- [6], due to the large-scale process variations and aggressive design specifications at advanced technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Correlated Bayesian Model Fusion

Wang

2016

Proceedings of the 53rd Annual Design Automation Conference

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Tunable circuit has emerged as a promising methodology to address the grand challenge posed by process variations. Efficient high-dimensional performance modeling of tunable analog/RF circuits is an important yet challenging task. In this paper, we propose a novel performance modeling approach for tunable circuits, referred to as Correlated Bayesian Model Fusion (C-BMF). The key idea is to encode the correlation information for both model template and coefficient magnitude among different knob configurations by using a unified prior distribution. The prior distribution is then combined with a few simulation samples via Bayesian inference to efficiently determine the unknown model coefficients. Two circuit examples designed in a commercial 32nm SOI CMOS process demonstrate that C-BMF achieves more than 2× cost reduction over the traditional state-ofthe-art modeling technique without surrendering any accuracy.

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