Statistical security analysis of AES with X‐tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure

Abstract

Advanced encryption standard (AES) crypto-algorithm design can be implemented in software and hardware. No known attacks are available that can break the AES with brute force or cryptanalysis in finite time. However, when the AES is implemented in hardware, test infrastructure such as scan chain, stimuli decompressor, response compactor and built-in selftest (BIST) are included in the normal design for making the crypto-chip easily testable after manufacturing. This test infrastructure is highly susceptible to attacks. The attacker may misuse the scan-chain content for the retrieval of secret key from AES hardware. In this study, the authors investigated scan-chain attack based on different distributions of key-related flipflops of AES hardware implementation with X-tolerant response compactor-based test infrastructure. The modular exponentiation security scheme as a counter measure against test infrastructure attacks is proposed. In this study, the statistical security analyses are performed with and without the proposed countermeasure in case of AES hardware followed by X-tolerant test response compactor. The experimental result shows that the proposed countermeasure thwarts the attack with almost constant rate for different distributions of key-related flops in the scan-chain, and hence it is not dependent on the nature of scan-chain architecture design.