Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

Abstract

Abstract-As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Temperature Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion theory such that it can cover the natural variations encountered in nanoscale MOSFET circuits. Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. A mitigation technology for minimizing the NBTI aging is also demonstrated by taking advantage of the independent-gate FinFET device structure using threshold voltage adjustment. We evaluated the impact of our proposal on the RAM stability by means of SPICE simulations with the BSIM-IMG Model for 22nm FinFET devices. Our simulations conducted at an accelerated temperature 125• C for 10 8 seconds (∼3 years) indicate that a V th compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective. However, the READ Static Noise Margin (SNM) experiences an insignificant decrease over the 3 years time span in the presence of a V th compensation, while without compensation it decreases by a x4 factor. Thus we can conclude that the proposed technique can improve the stability of SRAM array during its operational life, hence improve the performance and reliability of the system.

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

“…The constant current method for extracting V T N and V T P was applied in these simulations with 100 nA µm −1 of drain current and V DS = 1.2 V Q it is generated during the negative BTI stress voltage V G S while Q ox is neglected. The variations of D it with V G S and time t are implemented in ASC trough the formula D it = A · (V G S − V th0 ) 2/3 · t 1/6[22] with constant A = 10 11 cm −2 eV −1 arbitrarily chosen in this work to enhance the aging effects. The time dependent functions of D it calculated for different V G S are shown on secondary axis ofFig.…”

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

“…A crucial datum obtained by device level research is that NBTI actually depends on process parameters including toxe, L, W in MOSFETs, and toxe, L, hfin, tfin in FinFETs, so that process variations actually interfere with the aging statistical impact [7][10] [25]. In [9], for CMOS gates, L, W, and toxe are taken into account in estimating the gate aging effects, to conclude that NBTI circuit aging can be severely affected by the magnitude of the process variations.…”

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

“…As can be seen, compared to a traditional planar transistor, the FinFET structure is designed with additional fin sidewall surface with higher availability of Si-H bonds [21] [41], implying larger chances of forming interface trap and consequently expediting the device degradation.…”

“…One of the most daunting conundrums is the increasing aging rate caused by negative bias temperature instability (NBTI). Recent experimental studies demonstrate that FinFET transistors are more vulnerable to NBTI, leading to a shorter lifetime than a planar device [21] [41]. The NBTI aging rate is evaluated by the increase of delay on the critical path after a certain amount of service time.…”