Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Pandey, .; Glesner,

doi:10.1109/dac.2006.229278

Cited by 5 publications

(13 citation statements)

References 13 publications

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“…During the scheduling, the slack of each task c ∈ C is exploited to share the bus(es). The formulation of the optimization problem is given as follows [11], [9], minimize: X subject to,…”

Section: Bus Synthesismentioning

confidence: 99%

“…In [6] a synthesis flow which supports shared buses and point-to-point connection templates was presented. In [9], [10] an energy conscious on-chip bus synthesis technique was presented. All the above techniques are for synthesizing on-chip bus architectures, however, non of them synthesizes memories.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, the bus synthesis algorithm is based on the approach proposed in [11], [9], which synthesizes a custom bus architecture. The synthesis problem is formulated as an optimization problem and finds the optimal bus widths and the number of buses.…”

Section: Introductionmentioning

confidence: 99%

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Co-synthesis of custom on-chip bus and memory for MPSoC architectures

Pandey

Genz

Drechsler

2007

2007 IFIP International Conference on Very Large Scale Integration

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Abstract-The advancement in process technology has made it possible to integrate multiple processing modules on a single chip. As a result of this, there is a sharp increase of communication traffic on the communication bus architecture. In this case, the traditional single bus based architecture may fail to meet the real-time constraints. The major concern of the scaled technology is an effect of coupling capacitance due to the trend of shrinking pitches, i.e., the distance between two wires. Its consequence is higher crosstalk noise, which degrades the signal integrity and modifies the power consumption of the wires. This motivates the synthesis of a custom on-chip bus architecture, which is efficient in terms of power and performance. Further, the memory of a complex multiprocessor system has a significant contribution to power and delay.In this paper, we present a co-synthesis of on-chip buses and memories, which finds an optimal bus architecture, memory sizes, and the number of memories. The bus synthesis problem is formulated as an optimization problem as proposed in [11], [9]. Then it is solved efficiently using an optimization tool. The memory synthesis problem is based on the graph partitioning algorithm, which partitions a data dependency task graph into a set of sub graphs with the minimum number of data dependencies called cut. The experiments carried out on the real-life multimedia applications validate the proposed technique for the co-synthesis of bus architecture and memory.

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“…During the scheduling, the slack of each task c ∈ C is exploited to share the bus(es). The formulation of the optimization problem is given as follows [11], [9], minimize: X subject to,…”

Section: Bus Synthesismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Co-synthesis of custom on-chip bus and memory for MPSoC architectures

Pandey

Genz

Drechsler

2007

2007 IFIP International Conference on Very Large Scale Integration

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“…Furthermore, it explores a trade-off between communication resources and power consumption during bus synthesis. The bus synthesis technique in our work is similar to [14], [15], however, the proposed approach in [14], [15] was limited to a task with a deterministic arrival time. Thus, the synthesized bus architecture may fail to meet the real-time constraint if the arrival time and rate of tasks is random due to the partial re-configuration of a system.…”

mentioning

confidence: 99%

“…However, the approach is only used for the power optimization of a post synthesis bus architecture. Recently, a simultaneous bus synthesis and voltage scaling technique was presented in [14], [15], which finds the optimal bus width and the number of buses. Furthermore, it explores a trade-off between communication resources and power consumption during bus synthesis.…”

mentioning

confidence: 99%

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

Pandey

Drechsler²

2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-task arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with dynamic workload. In this context, the traditional application specific bus architectures may fail to meet the real-time constraints. Thus, to incorporate the random behavior of on-chip communication, this work proposes an approach to synthesize an on-chip bus architecture, which is robust for a given distributions of random tasks. The randomness of communication tasks is characterized by three main parameters which are the average task arrival rate, the average inter-task arrival time, and the data size. For synthesis, an on-chip bus requirement is guided by the worst-case performance need, while the dynamic voltage scaling technique is used to save energy when the workload is low or timing slack is high. This, in turn, results in an effective utilization of communication resources under variable workload.

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Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Pandey¹,

Drechsler²

2008

2008 Design, Automation and Test in Europe

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In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.

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Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Cited by 5 publications

References 13 publications

Co-synthesis of custom on-chip bus and memory for MPSoC architectures

Co-synthesis of custom on-chip bus and memory for MPSoC architectures

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

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