Statistical MOSFET Modeling Methodology for Cryogenic Conditions

Kabaoglu, Aykut; Solmaz, Nergiz Şahin; Ilik, Sadik; Uzun, Yasemin; Yelten, Mustafa Berke

doi:10.1109/ted.2018.2877942

Cited by 22 publications

(5 citation statements)

References 21 publications

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“…There is a need for a physics based, accurate, scalable, robust MOSFET BSIM compatible model for circuit simulation and technology assessment. Some of the recent publications [16][17][18][19][20] demonstrate similar modelling but the devices are on matured technology nodes (E.g., 180nm).…”

Section: Introductionmentioning

confidence: 86%

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in cryogenic operation of digital logic. In this paper, we analyze digital standard cells in 28nm High-K Metal Gate (HKMG) CMOS foundry Process Design Kit (PDK). We have developed BSIM4 models of cryogenic CMOS and calibrated with experimental measurements. Since, low temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this paper, we present inverter static and dynamic characteristics and multiple Ring Oscillator(RO) structures. The simulation study shows that we can achieve 28%(FO4-RO) -59%(NAND3-RO) higher performance under iso-VDD scenario and up to 90% improvement in the Energy Delay Product (EDP) under isooverdrive scenario at 6K compared to room temperature.

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Section: Introductionmentioning

confidence: 86%

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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show abstract

“…In order to achieve this task, the modeling methodology, shown in figure 1, has been adopted. This methodology is an improved version of the approach we proposed in [13], with the added capability of accurately estimating the sub-threshold characteristics of MOSFETs.…”

Section: Modeling Methodologymentioning

confidence: 99%

“…For this purpose, a MATLAB routine is implemented that can run Cadence Spectre simulations iteratively. In order for the algorithm to start operating, biasing conditions, channel geometry and I−V measurements of devices as well as the the environment temperature should be provided as input [13].…”

Section: Modeling Methodologymentioning

confidence: 99%

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Variability-aware cryogenic models of mosfets: validation and circuit design

Kabaoglu¹,

Şahin-Solmaz²,

Ilik³

et al. 2019

Semicond. Sci. Technol.

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In this paper, a metal-oxide-semiconductor-field-effect-transistor modeling methodology for cryogenic conditions has been extensively verified through device measurements performed on a cryogenic probe station that was cooled by liquid nitrogen (−196 °C). The approach is valid for all operating regions (including the sub-threshold mode). The developed model can estimate I D -V GS and I D -V DS curves of transistors having different channel lengths and widths with an error of less than 5%. Statistical analysis of cryogenic measurements is used to introduce the variation levels around the nominal cryogenic operation to identify the impact of process variations at cryogenic conditions. Models adjusted to various temperatures between −196 °C and −40 °C have been developed for applications requiring different cryogenic operation conditions. Experimental data collected from a ring oscillator is employed to visualize the model performance in estimating the cryogenic characteristics of a typical integrated circuit. It is shown that the frequency of the ring oscillator is correctly simulated using the proposed cryogenic models.

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“…In order to experimentally characterize the cryogenic properties of low V TH nMOSFETs, a test chip has been fabricated that contains several types of transistors, including low V TH nMOSFETs (Fig. 1) [11]. Here, four pads are assigned to every transistor corresponding each to one terminal of the transistor.…”

Section: Test Chip For Experimental Characterization and Measurementioning

confidence: 99%

Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETs

Yelten

2019

Balkan Journal of Electrical and Computer Engineering

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Cryogenic electronics has grown in its widespread use for various technological applications. Particularly, CMOS devices and circuits are more frequently used in such systems due to their dominance in the electronics industry. At cryogenic temperatures, characteristics of CMOS devices vary, which should be characterized with measurements. In this paper, the changes in the electronic behavior of a low threshold voltage (VTH) n-channel MOSFET (nMOSFET) are captured experimentally. The results are then compared with the measurements of a regular nMOSFET having the same channel width and length. It is shown that although the VTH increase of both transistors is at the same amount, this value corresponds to a more significant percentage of the nominal threshold voltage for the low VTH nMOSFET.

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Statistical MOSFET Modeling Methodology for Cryogenic Conditions

Cited by 22 publications

References 21 publications

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Variability-aware cryogenic models of mosfets: validation and circuit design

Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETs

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