Statistical Modeling based on extensive TCAD simulations Proposed methodology for extraction of Fast/Slow models and Statistical models

Vandenbossche, Eric; Kopalidis, George; Tack, M.; Schoenmaker, Wim

doi:10.1007/978-3-7091-6827-1_24

Cited by 2 publications

(1 citation statement)

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“…Despite this, n-to-p tracking characteristics are predictable based on mature hardware from older technology nodes and the particular performance step-up plan in each newer planar SOI technology. This has been facilitated by statistical technology computer-aided design (TCAD), which has been used to guide n-to-p tracking predictions and to assess corner performance impact in the early stages of technology development for planar CMOS technologies [10]- [13].…”

Section: Introductionmentioning

confidence: 99%

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

Deng

Rahman

Thoma

et al. 2015

IEEE Trans. Electron Devices

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In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.Index Terms-Integrated circuits design, MOSFETs, semiconductor device modeling, variation aware timing. 0018-9383

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Section: Introductionmentioning

confidence: 99%

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

Deng

Rahman

Thoma

et al. 2015

IEEE Trans. Electron Devices

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Statistical SPICE analysis of a 0.18 μm CMOS digital/analog technology during process development

Rankin¹,

Ng²,

Ee³

et al.

ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153)

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This paper gives details of a methodology to extract statistical SPICE models on a developing deep sub micron CMOS technology. The approach uses a TCAD framework which integrates process, device, parameter extraction, and statistics software. The TCAD tools are calibrated by physical and electrical measurements on transistor test structures with different channel lengths. Once calibrated, a Monte Carlo experiment is run on all process control input parameters with realistic variations and the results then compared to in-line and E-test distributions. When satisfied that the variance in TCAD and measured distributions match, the framework can be used to extract BSIM3v3.2 parameters to generate statistical models. Multivariate statistics is used to determine the key process parameters which need to be controlled in-line to minimize device variation. This methodology is demonstrated using Chartered Semiconductor Manufacturing Ltd's 0.18pm CMOS core logic technology. I. MOTIVATIONThe main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models [ l ] for a developing deep sub micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. Another goal from the statistical analysis is to identify key in-line process parameters which need to be monitored to minimise device variation. The ability to produce early statistical models by this method has the potential to help process optimisation and improve product yield. A calibrated TCAD framework can also be used to predict next generation SPICE models.NMOS device which has a drawn gate length of 0 . 1 8~m and a physical thin gate oxide thickness of 30A. TCAD CALIBRATIONTCAD is a key activity for the development and understanding of advanced CMOS technology. The main goal of characterizing a CMOS process using TCAD is to develop two decks (NMOS and PMOS) which model the effects on I-V curves for different channel lengths. Therefore, it is critical to model the non-uniform vertical and lateral channel profiles for different device types which need to be calibrated for each individual technology in order to model short channel effects on transistor threshold voltage. To calibrate process simulations in-line measurements from development silicon and SIMS measurements are used to match layer thickness' and doping profiles. Device simulations were calibrated using the first revision of transistor measurement characteristics from carefully designed modelling test structures (see figure 2), suitable for SPICE extraction, and initial E-test data.

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Statistical Modeling based on extensive TCAD simulations Proposed methodology for extraction of Fast/Slow models and Statistical models

Cited by 2 publications

References 0 publications

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

Statistical SPICE analysis of a 0.18 μm CMOS digital/analog technology during process development

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