Statistical investigation of the floating gate memory cell leakage through high-k interpoly dielectrics and its impact on scalability and reliability

Abstract

In this work, we investigate the floating gate (FG) cell leakage through high-k interpoly dielectrics (IPDs) using a statistical approach. The impact of defects on stack scalability is addressed from a NAND technology perspective. Trap distributions are extracted from high-temperature retention tests carried out on Al 2 O 3 -based IPDs. Extracted material parameters are used together with a newly developed Monte-Carlo leakage/retention simulator in order to investigate the behavior of single-and multitrap leakage paths on large Flash memory arrays and predict the failure rate.

Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies

“…Independent retention modeling of TANOS required the presence of an Al 2 O 3 defect band with identical energy level and trap density as found with TSCIS [42], and also yielded an Si 3 N 4 charge profile that matched very well the TSCIS result [41], thus confirming the consistency of the technique. As a result the technique can be used to predict the retention performance of memory cells.…”

A consistent model for oxide trap profiling with the Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique

“…Similar models based on S-R-H and direct tunneling analysis have been applied to other techniques also, such as conventional charge pumping [10], pulsed I d -V g technique [11], gate leakage current [15], noise analysis [18], and tunnel-current deep level transient spectroscopy (T-CDLTS) [24].…”

“…A Metal Inserted Poly-Silicon (MIPS) [14] gate electrode was used. For this device, the conduction band offset of the Al 2 O 3 dielectric is measured as 2.6 eV using photoemission, the effective mass is fixed at 0.35m 0 obtained from a number of fits to tunneling leakage current curves [15]. To decide the cross section, our model is first applied to the experimental data from 'Variable T charge -T discharge Amplitude Charge pumping (VT 2 ACP) [16]', where t ch from 1 ls to a few ms enables us to see the SiO 2 /Al 2 O 3 interface.…”

Experimental evidence and modeling of two types of electron traps in Al2O3 for nonvolatile memory applications

“…[3][4][5][6][7][8][9][10] Due to its high dielectric constant (j Al2O3 $ 9), the control gate-floating gate coupling ratio is increased without reducing the IPD's physical thickness. In addition, the band gap of Al 2 O 3 ($9 eV) is high in comparison to other high-j dielectrics, improving data retention.…”